Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

[Chen-Yu Tsai]

On Thu, Feb 18, 2021 at 4:06 PM Icenowy Zheng <icenowy@xxxxxxx> wrote:
>
>
>
> 于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard <maxime@xxxxxxxxxx> 写到:
> >Hi,
> >
> >On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> >> Previously the variable rate audio pll output was fixed to a divider
> >of
> >> four. This is unfortunately incompatible with generating commonly
> >used
> >> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> >> This commit adds support for arbitrary audio pll output dividers to
> >fix
> >> that.
> >>
> >> Signed-off-by: Tobias Schramm <t.schramm@xxxxxxxxxxx>
> >
> >It's not really clear to me how that would help.
>
> We have introducee SDM-based accurate audio PLL on several
> other SoCs. Some people is quite sensitive about audio-related things.

Right. What you really want is the SDM-based fractional clock support.
Just look at the other drivers.

> >
> >The closest frequency we can provide for 24.576MHz would be 24580645
> >Hz,
> >with N = 127, M = 31 and P = 4, so it would work with what we have
> >already?

Correct. And that is still slightly off. It's even worse for the 44.1khz
family.


ChenYu

> >Maxime
>
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