Re: [PATCH v21 05/26] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states

[Borislav Petkov]

On Wed, Feb 17, 2021 at 02:27:09PM -0800, Yu-cheng Yu wrote:
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 546d6ecf0a35..fae6b3ea1f6d 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -933,4 +933,23 @@
>  #define MSR_VM_IGNNE                    0xc0010115
>  #define MSR_VM_HSAVE_PA                 0xc0010117
>  
> +/* Control-flow Enforcement Technology MSRs */
> +#define MSR_IA32_U_CET		0x6a0 /* user mode cet setting */
> +#define MSR_IA32_S_CET		0x6a2 /* kernel mode cet setting */
> +#define CET_SHSTK_EN		BIT_ULL(0)
> +#define CET_WRSS_EN		BIT_ULL(1)
> +#define CET_ENDBR_EN		BIT_ULL(2)
> +#define CET_LEG_IW_EN		BIT_ULL(3)
> +#define CET_NO_TRACK_EN		BIT_ULL(4)
> +#define CET_SUPPRESS_DISABLE	BIT_ULL(5)
> +#define CET_RESERVED		(BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
> +#define CET_SUPPRESS		BIT_ULL(10)
> +#define CET_WAIT_ENDBR		BIT_ULL(11)
> +
> +#define MSR_IA32_PL0_SSP	0x6a4 /* kernel shadow stack pointer */
> +#define MSR_IA32_PL1_SSP	0x6a5 /* ring-1 shadow stack pointer */
> +#define MSR_IA32_PL2_SSP	0x6a6 /* ring-2 shadow stack pointer */
> +#define MSR_IA32_PL3_SSP	0x6a7 /* user shadow stack pointer */
> +#define MSR_IA32_INT_SSP_TAB	0x6a8 /* exception shadow stack table */

When you look at the formatting in that file and the MSR numbers in it, what
stops you from formatting your addition the same way?

-- 
Regards/Gruss,
    Boris.

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