Re: [PATCH] clk: imx8mq: Correct the pcie1 sels
From: Stephen Boyd
Date: Tue Mar 30 2021 - 22:18:23 EST
Quoting Richard Zhu (2021-03-15 01:17:48)
> - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
> Change the sys2_pll_500m to sys2_pll_50m.
> - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from
> "sys2_pll_250m" to "sys2_pll_333m".
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
Any Fixes tag?