Re: [PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities

[Liang, Kan]

On 4/8/2021 9:40 AM, Peter Zijlstra wrote:
> > @@ -4330,7 +4347,7 @@ static int intel_pmu_check_period(struct perf_event *event, u64 value)
> >   
> >   static int intel_pmu_aux_output_match(struct perf_event *event)
> >   {
> > -	if (!x86_pmu.intel_cap.pebs_output_pt_available)
> > +	if (!intel_pmu_has_cap(event, PERF_CAP_PT_IDX))
> >   		return 0;
> >   
> >   	return is_intel_pt_event(event);
> these sites can have !event->pmu ?


I don't think the event->pmu can be NULL, but it could be pt_pmu.pmu.
If so, it should be a problem.

I think I will still use the x86_pmu.intel_cap.pebs_output_pt_available 
here in V6. The worst case is that we lost the PEBS via PT support on 
the small core for now.

I guess Alexander may provide a separate patch later to enable the PEBS 
via PT support on the ADL small core.

Thanks,
Kan