Re: [PATCH V5 23/25] perf/x86/msr: Add Alder Lake CPU support

[Peter Zijlstra]

On Mon, Apr 05, 2021 at 08:11:05AM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> 
> PPERF and SMI_COUNT MSRs are also supported on Alder Lake.
> 
> The External Design Specification (EDS) is not published yet. It comes
> from an authoritative internal source.
> 
> The patch has been tested on real hardware.
> 
> Reviewed-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/events/msr.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
> index 680404c..c853b28 100644
> --- a/arch/x86/events/msr.c
> +++ b/arch/x86/events/msr.c
> @@ -100,6 +100,8 @@ static bool test_intel(int idx, void *data)
>  	case INTEL_FAM6_TIGERLAKE_L:
>  	case INTEL_FAM6_TIGERLAKE:
>  	case INTEL_FAM6_ROCKETLAKE:
> +	case INTEL_FAM6_ALDERLAKE:
> +	case INTEL_FAM6_ALDERLAKE_L:
>  		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
>  			return true;
>  		break;

If only it would be sanely enumerated... What about sapphire rapids?