[PATCH Part1 RFC v2 03/20] x86/sev: Add support for hypervisor feature VMGEXIT

[Brijesh Singh]

Version 2 of GHCB specification introduced advertisement of a features
that are supported by the hypervisor. Define the GHCB MSR protocol and NAE
for the hypervisor feature request and query the feature during the GHCB
protocol negotitation. See the GHCB specification for more details.

Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx>
---
 arch/x86/include/asm/sev-common.h | 17 +++++++++++++++++
 arch/x86/include/uapi/asm/svm.h   |  2 ++
 arch/x86/kernel/sev-shared.c      | 24 ++++++++++++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
index 9f1b66090a4c..8142e247d8da 100644
--- a/arch/x86/include/asm/sev-common.h
+++ b/arch/x86/include/asm/sev-common.h
@@ -51,6 +51,22 @@
 #define GHCB_MSR_AP_RESET_HOLD_RESULT_POS	12
 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK	0xfffffffffffff
 
+/* GHCB Hypervisor Feature Request */
+#define GHCB_MSR_HV_FEATURES_REQ	0x080
+#define GHCB_MSR_HV_FEATURES_RESP	0x081
+#define GHCB_MSR_HV_FEATURES_POS	12
+#define GHCB_MSR_HV_FEATURES_MASK	0xfffffffffffffUL
+#define GHCB_MSR_HV_FEATURES_RESP_VAL(v)	\
+	(((v) >> GHCB_MSR_HV_FEATURES_POS) & GHCB_MSR_HV_FEATURES_MASK)
+
+#define GHCB_HV_FEATURES_SNP		BIT_ULL(0)
+#define GHCB_HV_FEATURES_SNP_AP_CREATION			\
+		(BIT_ULL(1) | GHCB_HV_FEATURES_SNP)
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION		\
+		(BIT_ULL(2) | GHCB_HV_FEATURES_SNP_AP_CREATION)
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER		\
+		(BIT_ULL(3) | GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION)
+
 #define GHCB_MSR_TERM_REQ		0x100
 #define GHCB_MSR_TERM_REASON_SET_POS	12
 #define GHCB_MSR_TERM_REASON_SET_MASK	0xf
@@ -62,6 +78,7 @@
 
 #define GHCB_SEV_ES_REASON_GENERAL_REQUEST	0
 #define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED	1
+#define GHCB_SEV_ES_REASON_SNP_UNSUPPORTED	2
 
 #define GHCB_RESP_CODE(v)		((v) & GHCB_MSR_INFO_MASK)
 
diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h
index 554f75fe013c..7fbc311e2de1 100644
--- a/arch/x86/include/uapi/asm/svm.h
+++ b/arch/x86/include/uapi/asm/svm.h
@@ -108,6 +108,7 @@
 #define SVM_VMGEXIT_AP_JUMP_TABLE		0x80000005
 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE		0
 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE		1
+#define SVM_VMGEXIT_HYPERVISOR_FEATURES		0x8000fffd
 #define SVM_VMGEXIT_UNSUPPORTED_EVENT		0x8000ffff
 
 #define SVM_EXIT_ERR           -1
@@ -215,6 +216,7 @@
 	{ SVM_VMGEXIT_NMI_COMPLETE,	"vmgexit_nmi_complete" }, \
 	{ SVM_VMGEXIT_AP_HLT_LOOP,	"vmgexit_ap_hlt_loop" }, \
 	{ SVM_VMGEXIT_AP_JUMP_TABLE,	"vmgexit_ap_jump_table" }, \
+	{ SVM_VMGEXIT_HYPERVISOR_FEATURES,	"vmgexit_hypervisor_feature" }, \
 	{ SVM_EXIT_ERR,         "invalid_guest_state" }
 
 
diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c
index 48a47540b85f..874f911837db 100644
--- a/arch/x86/kernel/sev-shared.c
+++ b/arch/x86/kernel/sev-shared.c
@@ -20,6 +20,7 @@
  * out when the .bss section is later cleared.
  */
 static u16 ghcb_version __section(".data") = 0;
+static u64 hv_features __section(".data") = 0;
 
 static bool __init sev_es_check_cpu_features(void)
 {
@@ -49,6 +50,26 @@ static void __noreturn sev_es_terminate(unsigned int reason)
 		asm volatile("hlt\n" : : : "memory");
 }
 
+static bool ghcb_get_hv_features(void)
+{
+	u64 val;
+
+	/* The hypervisor features are available from version 2 onward. */
+	if (ghcb_version < 2)
+		return true;
+
+	sev_es_wr_ghcb_msr(GHCB_MSR_HV_FEATURES_REQ);
+	VMGEXIT();
+
+	val = sev_es_rd_ghcb_msr();
+	if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FEATURES_RESP)
+		return false;
+
+	hv_features = GHCB_MSR_HV_FEATURES_RESP_VAL(val);
+
+	return true;
+}
+
 static bool sev_es_negotiate_protocol(void)
 {
 	u64 val;
@@ -67,6 +88,9 @@ static bool sev_es_negotiate_protocol(void)
 
 	ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX);
 
+	if (!ghcb_get_hv_features())
+		return false;
+
 	return true;
 }
 
-- 
2.17.1