drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:6679:13: warning: stack frame size of 2656 bytes in function 'UseMinimumDCFCLK'

From: kernel test robot
Date: Wed May 05 2021 - 18:03:29 EST

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Hi Alex,

First bad commit (maybe != root cause):

tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: d665ea6ea86c785760ee4bad4543dab3267ad074
commit: 20f2ffe504728612d7b0c34e4f8280e34251e704 drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
date: 6 months ago
config: powerpc-randconfig-r016-20210505 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 8f5a2a5836cc8e4c1def2bdeb022e7b496623439)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=20f2ffe504728612d7b0c34e4f8280e34251e704
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 20f2ffe504728612d7b0c34e4f8280e34251e704
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:1917:13: warning: stack frame size of 9072 bytes in function 'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation' [-Wframe-larger-than=]
static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3641:6: warning: stack frame size of 9104 bytes in function 'dml30_ModeSupportAndSystemConfigurationFull' [-Wframe-larger-than=]
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:6679:13: warning: stack frame size of 2656 bytes in function 'UseMinimumDCFCLK' [-Wframe-larger-than=]
static void UseMinimumDCFCLK(
^
3 warnings generated.
--
^
<scratch space>:155:1: note: expanded from here
DCN_BASE__INST0_SEG3
^
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:373:52: note: expanded from macro 'DCN_BASE__INST0_SEG3'
#define DCN_BASE__INST0_SEG3 0x00009000
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:753:3: note: previous initialization is here
HWSEQ_DCN30_REG_LIST()
^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:341:2: note: expanded from macro 'HWSEQ_DCN30_REG_LIST'
HWSEQ_DCN2_REG_LIST(),\
^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:244:2: note: expanded from macro 'HWSEQ_DCN2_REG_LIST'
SR(MPC_CRC_RESULT_C), \
^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:247:15: note: expanded from macro 'SR'
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:242:25: note: expanded from macro 'BASE_INNER'
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
^
<scratch space>:170:1: note: expanded from here
DCN_BASE__INST0_SEG3
^
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:373:52: note: expanded from macro 'DCN_BASE__INST0_SEG3'
#define DCN_BASE__INST0_SEG3 0x00009000
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:753:3: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
HWSEQ_DCN30_REG_LIST()
^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:357:2: note: expanded from macro 'HWSEQ_DCN30_REG_LIST'
SR(MPC_CRC_RESULT_AR), \
^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:247:15: note: expanded from macro 'SR'
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:244:19: note: expanded from macro 'BASE'
#define BASE(seg) BASE_INNER(seg)
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:242:25: note: expanded from macro 'BASE_INNER'
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
^
<scratch space>:159:1: note: expanded from here
DCN_BASE__INST0_SEG3
^
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:373:52: note: expanded from macro 'DCN_BASE__INST0_SEG3'
#define DCN_BASE__INST0_SEG3 0x00009000
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:753:3: note: previous initialization is here
HWSEQ_DCN30_REG_LIST()
^~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:341:2: note: expanded from macro 'HWSEQ_DCN30_REG_LIST'
HWSEQ_DCN2_REG_LIST(),\
^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:245:2: note: expanded from macro 'HWSEQ_DCN2_REG_LIST'
SR(MPC_CRC_RESULT_AR), \
^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:247:15: note: expanded from macro 'SR'
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:242:25: note: expanded from macro 'BASE_INNER'
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
^
<scratch space>:174:1: note: expanded from here
DCN_BASE__INST0_SEG3
^
drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:373:52: note: expanded from macro 'DCN_BASE__INST0_SEG3'
#define DCN_BASE__INST0_SEG3 0x00009000
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:875:6: warning: no previous prototype for function 'dcn30_dpp_destroy' [-Wmissing-prototypes]
void dcn30_dpp_destroy(struct dpp **dpp)
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:875:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
void dcn30_dpp_destroy(struct dpp **dpp)
^
static
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:992:16: warning: no previous prototype for function 'dcn30_hubbub_create' [-Wmissing-prototypes]
struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:992:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
^
static
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1143:24: warning: no previous prototype for function 'dcn30_stream_encoder_create' [-Wmissing-prototypes]
struct stream_encoder *dcn30_stream_encoder_create(
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1143:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
struct stream_encoder *dcn30_stream_encoder_create(
^
static
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1175:19: warning: no previous prototype for function 'dcn30_hwseq_create' [-Wmissing-prototypes]
struct dce_hwseq *dcn30_hwseq_create(
^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1175:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
struct dce_hwseq *dcn30_hwseq_create(
^
static
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1959:13: warning: stack frame size of 3216 bytes in function 'dcn30_internal_validate_bw' [-Wframe-larger-than=]
static bool dcn30_internal_validate_bw(
^
116 warnings generated.

Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for HOTPLUG_PCI_POWERNV
Depends on PCI && HOTPLUG_PCI && PPC_POWERNV && EEH
Selected by
- OCXL && PPC_POWERNV && PCI && EEH

vim +/UseMinimumDCFCLK +6679 drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c

6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6677
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6678
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 @6679 static void UseMinimumDCFCLK(
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6680 struct display_mode_lib *mode_lib,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6681 int MaxInterDCNTileRepeaters,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6682 int MaxPrefetchMode,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6683 double FinalDRAMClockChangeLatency,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6684 double SREnterPlusExitTime,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6685 int ReturnBusWidth,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6686 int RoundTripPingLatencyCycles,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6687 int ReorderingBytes,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6688 int PixelChunkSizeInKByte,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6689 int MetaChunkSize,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6690 bool GPUVMEnable,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6691 int GPUVMMaxPageTableLevels,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6692 bool HostVMEnable,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6693 int NumberOfActivePlanes,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6694 double HostVMMinPageSize,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6695 int HostVMMaxNonCachedPageTableLevels,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6696 bool DynamicMetadataVMEnabled,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6697 enum immediate_flip_requirement ImmediateFlipRequirement,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6698 bool ProgressiveToInterlaceUnitInOPP,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6699 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6700 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6701 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6702 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6703 int VTotal[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6704 int VActive[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6705 int DynamicMetadataTransmittedBytes[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6706 int DynamicMetadataLinesBeforeActiveRequired[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6707 bool Interlace[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6708 double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6709 double RequiredDISPCLK[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6710 double UrgLatency[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6711 unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6712 double ProjectedDCFCLKDeepSleep[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6713 double MaximumVStartup[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6714 double TotalVActivePixelBandwidth[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6715 double TotalVActiveCursorBandwidth[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6716 double TotalMetaRowBandwidth[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6717 double TotalDPTERowBandwidth[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6718 unsigned int TotalNumberOfActiveDPP[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6719 unsigned int TotalNumberOfDCCActiveDPP[][2],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6720 int dpte_group_bytes[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6721 double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6722 double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6723 int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6724 int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6725 int BytePerPixelY[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6726 int BytePerPixelC[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6727 int HTotal[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6728 double PixelClock[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6729 double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6730 double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6731 double MetaRowBytes[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6732 bool DynamicMetadataEnable[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6733 double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6734 double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6735 double ReadBandwidthLuma[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6736 double ReadBandwidthChroma[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6737 double DCFCLKPerState[],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6738 double DCFCLKState[][2])
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6739 {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6740 double NormalEfficiency = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6741 double PTEEfficiency = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6742 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6743 unsigned int i, j, k;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6744
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6745 NormalEfficiency = (HostVMEnable == true ? PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6746 : PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly) / 100.0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6747 PTEEfficiency = (HostVMEnable == true ? PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6748 / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData : 1.0);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6749 for (i = 0; i < mode_lib->soc.num_states; ++i) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6750 for (j = 0; j <= 1; ++j) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6751 double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX] = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6752 double PrefetchPixelLinesTime[DC__NUM_DPP__MAX] = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6753 double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX] = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6754 double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX] = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6755 double MinimumTWait = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6756 double NonDPTEBandwidth = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6757 double DPTEBandwidth = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6758 double DCFCLKRequiredForAverageBandwidth = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6759 double ExtraLatencyBytes = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6760 double ExtraLatencyCycles = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6761 double DCFCLKRequiredForPeakBandwidth = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6762 int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6763 double MinimumTvmPlus2Tr0 = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6764
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6765 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6766 for (k = 0; k < NumberOfActivePlanes; ++k) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6767 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6768 + NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6769 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6770
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6771 for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6772 NoOfDPPState[k] = NoOfDPP[i][j][k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6773 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6774
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6775 MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6776 NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6777 DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ?
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6778 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6779 DCFCLKRequiredForAverageBandwidth = dml_max3(ProjectedDCFCLKDeepSleep[i][j],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6780 (NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth / (MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6781 (NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency / ReturnBusWidth);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6782
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6783 ExtraLatencyBytes = CalculateExtraLatencyBytes(ReorderingBytes, TotalNumberOfActiveDPP[i][j], PixelChunkSizeInKByte, TotalNumberOfDCCActiveDPP[i][j],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6784 MetaChunkSize, GPUVMEnable, HostVMEnable, NumberOfActivePlanes, NoOfDPPState, dpte_group_bytes,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6785 PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6786 HostVMMinPageSize, HostVMMaxNonCachedPageTableLevels);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6787 ExtraLatencyCycles = RoundTripPingLatencyCycles + 32 + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6788 for (k = 0; k < NumberOfActivePlanes; ++k) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6789 double DCFCLKCyclesRequiredInPrefetch = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6790 double ExpectedPrefetchBWAcceleration = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6791 double PrefetchTime = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6792
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6793 PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6794 + PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6795 DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6796 / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * DPTEBytesPerRow[i][j][k] / PTEEfficiency
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6797 / NormalEfficiency / ReturnBusWidth + 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6798 PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6799 ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k]) / (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6800 DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6801 UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6802 PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait - UrgLatency[i] * ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6803 : GPUVMMaxPageTableLevels - 2) * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6804
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6805 if (PrefetchTime > 0) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6806 double ExpectedVRatioPrefetch = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6807 ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6808 DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6809 * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6810 if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6811 DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6812 + NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / ReturnBusWidth;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6813 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6814 } else {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6815 DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6816 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6817 if (DynamicMetadataEnable[k] == true) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6818 double TsetupPipe = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6819 double TdmbfPipe = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6820 double TdmsksPipe = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6821 double TdmecPipe = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6822 double AllowedTimeForUrgentExtraLatency = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6823
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6824 CalculateDynamicMetadataParameters(
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6825 MaxInterDCNTileRepeaters,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6826 RequiredDPPCLK[i][j][k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6827 RequiredDISPCLK[i][j],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6828 ProjectedDCFCLKDeepSleep[i][j],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6829 PixelClock[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6830 HTotal[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6831 VTotal[k] - VActive[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6832 DynamicMetadataTransmittedBytes[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6833 DynamicMetadataLinesBeforeActiveRequired[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6834 Interlace[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6835 ProgressiveToInterlaceUnitInOPP,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6836 &TsetupPipe,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6837 &TdmbfPipe,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6838 &TdmecPipe,
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6839 &TdmsksPipe);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6840 AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TsetupPipe
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6841 - TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6842 if (AllowedTimeForUrgentExtraLatency > 0) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6843 DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(DCFCLKRequiredForPeakBandwidthPerPlane[k],
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6844 ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6845 } else {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6846 DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6847 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6848 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6849 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6850 DCFCLKRequiredForPeakBandwidth = 0;
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6851 for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6852 DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6853 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6854 MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ? (HostVMEnable == true ?
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6855 (GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0);
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6856 for (k = 0; k < NumberOfActivePlanes; ++k) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6857 double MaximumTvmPlus2Tr0PlusTsw = { 0 };
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6858 MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6859 if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6860 DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6861 } else {
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6862 DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth, 2 * ExtraLatencyCycles
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6863 / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6864 (2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6865 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6866 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6867 DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100)
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6868 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6869 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6870 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6871 }
6725a88f88a7e9 Bhawanpreet Lakha 2020-05-21 6872

:::::: The code at line 6679 was first introduced by commit
:::::: 6725a88f88a7e922e91c45bf83d320487810c192 drm/amd/display: Add DCN3 DML

:::::: TO: Bhawanpreet Lakha <Bhawanpreet.Lakha@xxxxxxx>
:::::: CC: Alex Deucher <alexander.deucher@xxxxxxx>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
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