Re: [PATCH V2 2/4] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL

[Peng Fan (OSS)]

Hi Rob,

On 2021/5/6 7:08, Rob Herring wrote:
> On Fri, Apr 30, 2021 at 01:27:44PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@xxxxxxx>
> >
> > Document the i.MX BLK_CTL with its devicetree properties.
> >
> > Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> > ---
> >   .../bindings/soc/imx/fsl,imx-blk-ctl.yaml     | 73 +++++++++++++++++++
> >   1 file changed, 73 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> > new file mode 100644
> > index 000000000000..a491b63de50c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-blk-ctl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP i.MX BLK_CTL
> > +
> > +maintainers:
> > +  - Peng Fan <peng.fan@xxxxxxx>
> > +
> > +description:
> > +  i.MX BLK_CTL is a conglomerate of different GPRs that are
> > +  dedicated to a specific subsystem. It usually contains
> > +  clocks and resets amongst other things. Here we take the clocks
> > +  and resets as virtual PDs, the reason we could not take it as
> > +  clock provider is there is A/B lock issue between power domain
> > +  and clock.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - fsl,imx8mm-dispmix-blk-ctl
> > +          - fsl,imx8mm-vpumix-blk-ctl
> > +      - const: syscon
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#power-domain-cells":
> > +    const: 1
> > +
> > +  power-domains:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  power-domain-names:
> > +    minItems: 1
> > +    maxItems: 32
>
> Please describe why there's a range and we don't enumerate each entry.

Each BLK-CTL have different input power domains, they
have different names. So it is hard to write down each
power domain for each BLK-CTL.

Same to below clocks and clock-names.

Thanks,
Peng.

> > +
> > +  '#reset-cells':
> > +    const: 1
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/imx8mm-clock.h>
> > +
> > +    dispmix_blk_ctl: blk-ctl@32e28000 {
> > +      compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
> > +      reg = <0x32e28000 0x100>;
> > +      #power-domain-cells = <1>;
> > +      power-domains = <&pgc_dispmix>, <&pgc_mipi>;
> > +      power-domain-names = "dispmix", "mipi";
> > +      clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> > +               <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> > +      clock-names = "disp", "axi", "apb";
> > +    };
> > --
> > 2.30.0