Re: [PATCH v12 5/5] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func

[Tom Rix]

On 5/3/21 2:40 PM, Russ Weight wrote:
> Extend the MAX10 BMC Secure Update driver to include
> a function that returns 64 bits of additional HW specific
> data for errors that require additional information.
> This callback function enables the hw_errinfo sysfs
> node in the Intel Security Manager class driver.
>
> Signed-off-by: Russ Weight <russell.h.weight@xxxxxxxxx>

This looks fine.

Reviewed-by: Tom Rix <trix@xxxxxxxxxx>

> ---
> v12:
>    - No change
> v11:
>    - No change
> v10:
>    - No change
> v9:
>    - No change
> v8:
>    - Previously patch 6/6, otherwise no change
> v7:
>    - No change
> v6:
>    - Initialized auth_result and doorbell to HW_ERRINFO_POISON
>      in m10bmc_sec_hw_errinfo() and removed unnecessary if statements.
> v5:
>    - No change
> v4:
>    - No change
> v3:
>    - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_
>    - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update
>      driver"
> v2:
>    - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to
>      ensure that corresponding bits are set to 1 if we are unable
>      to read the doorbell or auth_result registers.
>    - Added m10bmc_ prefix to functions in m10bmc_iops structure
> ---
>   drivers/fpga/intel-m10-bmc-secure.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c
> index 9d45312001a3..bdf87ec125fe 100644
> --- a/drivers/fpga/intel-m10-bmc-secure.c
> +++ b/drivers/fpga/intel-m10-bmc-secure.c
> @@ -483,11 +483,33 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr)
>   	return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE;
>   }
>   
> +#define HW_ERRINFO_POISON	GENMASK(31, 0)
> +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr)
> +{
> +	struct m10bmc_sec *sec = smgr->priv;
> +	u32 auth_result = HW_ERRINFO_POISON;
> +	u32 doorbell = HW_ERRINFO_POISON;
> +
> +	switch (smgr->err_code) {
> +	case FPGA_SEC_ERR_HW_ERROR:
> +	case FPGA_SEC_ERR_TIMEOUT:
> +	case FPGA_SEC_ERR_BUSY:
> +	case FPGA_SEC_ERR_WEAROUT:
> +		m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
> +		m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result);
> +
> +		return (u64)doorbell << 32 | (u64)auth_result;
> +	default:
> +		return 0;
> +	}
> +}
> +
>   static const struct fpga_sec_mgr_ops m10bmc_sops = {
>   	.prepare = m10bmc_sec_prepare,
>   	.write_blk = m10bmc_sec_write_blk,
>   	.poll_complete = m10bmc_sec_poll_complete,
>   	.cancel = m10bmc_sec_cancel,
> +	.get_hw_errinfo = m10bmc_sec_hw_errinfo,
>   };
>   
>   static int m10bmc_secure_probe(struct platform_device *pdev)