drivers/net/wan/fsl_ucc_hdlc.c:305:17: sparse: sparse: incorrect type in argument 1 (different address spaces)

From: kernel test robot
Date: Wed May 12 2021 - 16:34:59 EST

Next
Previous
Messages

tree: config: arm-randconfig-s032-20210513 compiler: arm-linux-gnueabi-gcc reproduce:
wget # apt-get install sparse
# sparse # If you fix the issue, Reported-by: kernel

sparse warnings: >> drivers/net/w drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc drivers/net/wan/fsl_uc
vim +305 drivers/net/wan/
c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang be2e9415f8b366 Rasmus be2e9415f8b366 Rasmus c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 040b7c94e4ec58 David Gounaris 040b7c94e4ec58 David Gounaris 040b7c94e4ec58 David Gounaris 040b7c94e4ec58 David Gounaris 040b7c94e4ec58 David Gounaris 040b7c94e4ec58 David Gounaris c19b6d246a3562 Zhao Qiang 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 54e9e0874938ba Holger Brunck 54e9e0874938ba Holger Brunck 54e9e0874938ba Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck 067bb938dad61e Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 5b8aad93c52bdd Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 5b8aad93c52bdd Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 85deed56032b6c Holger Brunck c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang be2e9415f8b366 Rasmus 24a24d07d688a4 Colin Ian King c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 6396bb221514d2 Kees Cook 6396bb221514d2 Kees Cook c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 6396bb221514d2 Kees Cook 6396bb221514d2 Kees Cook c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang be2e9415f8b366 Rasmus c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang be2e9415f8b366 Rasmus c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 148587a59f6b85 Rasmus 148587a59f6b85 Rasmus 148587a59f6b85 Rasmus 148587a59f6b85 Rasmus 148587a59f6b85 Rasmus c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 045f77baf6b429 David Gounaris c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 750afb08ca7131 Luis 750afb08ca7131 Luis c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 5b8aad93c52bdd Holger Brunck c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang 5b8aad93c52bdd Holger Brunck c19b6d246a3562 Zhao Qiang 1efb597d8bf56c Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang c19b6d246a3562 Zhao Qiang
:::::: The code :::::: c19b6d246a35627c3a
:::::: TO: Zhao :::::: CC: David
---
0-DAY CI Kernel Attachment: Description: application/gzip message: Stefano Stabellini: "Re: [PATCH 1/2] xen/arm64: do not set SWIOTLB_NO_FORCE when swiotlb is required" message: Paul Menzel: "Re: [RESEND PATCH v2] iommu/amd: Fix extended features logging" sorted by: [ date ] [ thread ] [ subject ] [ author ] href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
3e070b022b5ceafa4f63f19
512ea55a9db8eb9f2e76959 sparse: use static inline for __chk_{user,io}_ptr()
(attached as .config)
(GCC) 9.3.0
rel="nofollow" href="https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross">https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
version: v0.6.3-341-g8af24329-dirty
href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5fc436f06eef54ef512ea55a9db8eb9f2e76959">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5fc436f06eef54ef512ea55a9db8eb9f2e76959
rel="nofollow" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
--no-tags linus master
e5fc436f06eef54ef512ea55a9db8eb9f2e76959
attached .config to linux build tree
PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=arm
kindly add following tag as appropriate
test robot <lkp@xxxxxxxxx>
(new ones prefixed by >>)
an/fsl_ucc_hdlc.c:305:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:305:17: sparse: expected void const volatile [noderef] __iomem *ptr
c_hdlc.c:305:17: sparse: got restricted __be16 *
c_hdlc.c:306:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got restricted __be32 * @@
c_hdlc.c:306:17: sparse: expected void volatile [noderef] __iomem *addr
c_hdlc.c:306:17: sparse: got restricted __be32 *
c_hdlc.c:316:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:316:17: sparse: expected void const volatile [noderef] __iomem *ptr
c_hdlc.c:316:17: sparse: got restricted __be16 *
c_hdlc.c:317:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got restricted __be32 * @@
c_hdlc.c:317:17: sparse: expected void volatile [noderef] __iomem *addr
c_hdlc.c:317:17: sparse: got restricted __be32 *
c_hdlc.c:368:29: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [usertype] @@ got restricted __be16 [usertype] @@
c_hdlc.c:368:29: sparse: expected unsigned short [usertype]
c_hdlc.c:368:29: sparse: got restricted __be16 [usertype]
c_hdlc.c:375:36: sparse: sparse: restricted __be16 degrades to integer
c_hdlc.c:398:12: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd [noderef] __iomem *bd @@ got struct qe_bd *curtx_bd @@
c_hdlc.c:398:12: sparse: expected struct qe_bd [noderef] __iomem *bd
c_hdlc.c:398:12: sparse: got struct qe_bd *curtx_bd
c_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
c_hdlc.c:421:20: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd [noderef] __iomem *[assigned] bd @@ got struct qe_bd *tx_bd_base @@
c_hdlc.c:421:20: sparse: expected struct qe_bd [noderef] __iomem *[assigned] bd
c_hdlc.c:421:20: sparse: got struct qe_bd *tx_bd_base
c_hdlc.c:423:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
c_hdlc.c:423:16: sparse: struct qe_bd [noderef] __iomem *
c_hdlc.c:423:16: sparse: struct qe_bd *
c_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:592:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *ptr @@ got restricted __be16 * @@
c_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
c_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
c_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
c_hdlc.c:723:29: sparse: sparse: dereference of noderef expression
c_hdlc.c:814:21: sparse: sparse: dereference of noderef expression
fsl_ucc_hdlc.c
2016-06-06 77
2016-06-06 78 static int uhdlc_init(struct ucc_hdlc_private *priv)
2016-06-06 79 {
2016-06-06 80 struct ucc_tdm_info *ut_info;
2016-06-06 81 struct ucc_fast_info *uf_info;
2016-06-06 82 u32 cecr_subblock;
2016-06-06 83 u16 bd_status;
2016-06-06 84 int ret, i;
2016-06-06 85 void *bd_buffer;
2016-06-06 86 dma_addr_t bd_dma_addr;
Villemoes 2019-11-28 87 s32 riptr;
Villemoes 2019-11-28 88 s32 tiptr;
2016-06-06 89 u32 gumr;
2016-06-06 90
2016-06-06 91 ut_info = priv->ut_info;
2016-06-06 92 uf_info = &ut_info->uf_info;
2016-06-06 93
2016-06-06 94 if (priv->tsa) {
2016-06-06 95 uf_info->tsa = 1;
2016-06-06 96 uf_info->ctsp = 1;
2018-09-03 97 uf_info->cds = 1;
2018-09-03 98 uf_info->ctss = 1;
2018-09-03 99 } else {
2018-09-03 100 uf_info->cds = 0;
2018-09-03 101 uf_info->ctsp = 0;
2018-09-03 102 uf_info->ctss = 0;
2016-06-06 103 }
2017-05-17 104
2017-05-17 105 /* This sets HPM register in CMXUCR register which configures a
2017-05-17 106 * open drain connected HDLC bus
2017-05-17 107 */
2017-05-17 108 if (priv->hdlc_bus)
2017-05-17 109 uf_info->brkpt_support = 1;
2017-05-17 110
2016-06-06 111 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
2016-06-06 112 UCC_HDLC_UCCE_TXB) << 16);
2016-06-06 113
2016-06-06 114 ret = ucc_fast_init(uf_info, &priv->uccf);
2016-06-06 115 if (ret) {
2016-06-06 116 dev_err(priv->dev, "Failed to init uccf.");
2016-06-06 117 return ret;
2016-06-06 118 }
2016-06-06 119
2016-06-06 120 priv->uf_regs = priv->uccf->uf_regs;
2016-06-06 121 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
2016-06-06 122
2016-06-06 123 /* Loopback mode */
2016-06-06 124 if (priv->loopback) {
2016-06-06 125 dev_info(priv->dev, "Loopback Mode\n");
2017-05-17 126 /* use the same clock when work in loopback */
2017-05-17 127 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
2017-05-17 128
2016-06-06 129 gumr = ioread32be(&priv->uf_regs->gumr);
2016-06-06 130 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
2016-06-06 131 UCC_FAST_GUMR_TCI);
2016-06-06 132 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
2016-06-06 133 iowrite32be(gumr, &priv->uf_regs->gumr);
2016-06-06 134 }
2016-06-06 135
2016-06-06 136 /* Initialize SI */
2016-06-06 137 if (priv->tsa)
2016-06-06 138 ucc_tdm_init(priv->utdm, priv->ut_info);
2016-06-06 139
2016-06-06 140 /* Write to QE CECR, UCCx channel to Stop Transmission */
2016-06-06 141 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
2016-06-06 142 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
2016-06-06 143 QE_CR_PROTOCOL_UNSPECIFIED, 0);
2016-06-06 144
2016-06-06 145 /* Set UPSMR normal mode (need fixed)*/
2016-06-06 146 iowrite32be(0, &priv->uf_regs->upsmr);
2016-06-06 147
2017-05-17 148 /* hdlc_bus mode */
2017-05-17 149 if (priv->hdlc_bus) {
2017-05-17 150 u32 upsmr;
2017-05-17 151
2017-05-17 152 dev_info(priv->dev, "HDLC bus Mode\n");
2017-05-17 153 upsmr = ioread32be(&priv->uf_regs->upsmr);
2017-05-17 154
2017-05-17 155 /* bus mode and retransmit enable, with collision window
2017-05-17 156 * set to 8 bytes
2017-05-17 157 */
2017-05-17 158 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
2017-05-17 159 UCC_HDLC_UPSMR_CW8;
2017-05-17 160 iowrite32be(upsmr, &priv->uf_regs->upsmr);
2017-05-17 161
2017-05-17 162 /* explicitly disable CDS & CTSP */
2017-05-17 163 gumr = ioread32be(&priv->uf_regs->gumr);
2017-05-17 164 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
2017-05-17 165 /* set automatic sync to explicitly ignore CD signal */
2017-05-17 166 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
2017-05-17 167 iowrite32be(gumr, &priv->uf_regs->gumr);
2017-05-17 168 }
2017-05-17 169
2016-06-06 170 priv->rx_ring_size = RX_BD_RING_LEN;
2016-06-06 171 priv->tx_ring_size = TX_BD_RING_LEN;
2016-06-06 172 /* Alloc Rx BD */
2016-06-06 173 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
2017-05-17 174 RX_BD_RING_LEN * sizeof(struct qe_bd),
2016-06-06 175 &priv->dma_rx_bd, GFP_KERNEL);
2016-06-06 176
2016-06-06 177 if (!priv->rx_bd_base) {
2016-06-06 178 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
2016-06-06 179 ret = -ENOMEM;
2016-07-15 180 goto free_uccf;
2016-06-06 181 }
2016-06-06 182
2016-06-06 183 /* Alloc Tx BD */
2016-06-06 184 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
2017-05-17 185 TX_BD_RING_LEN * sizeof(struct qe_bd),
2016-06-06 186 &priv->dma_tx_bd, GFP_KERNEL);
2016-06-06 187
2016-06-06 188 if (!priv->tx_bd_base) {
2016-06-06 189 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
2016-06-06 190 ret = -ENOMEM;
2016-07-15 191 goto free_rx_bd;
2016-06-06 192 }
2016-06-06 193
2016-06-06 194 /* Alloc parameter ram for ucc hdlc */
2017-05-22 195 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
2016-06-06 196 ALIGNMENT_OF_UCC_HDLC_PRAM);
2016-06-06 197
Villemoes 2019-11-28 198 if (priv->ucc_pram_offset < 0) {
2016-08-28 199 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
2016-06-06 200 ret = -ENOMEM;
2016-07-15 201 goto free_tx_bd;
2016-06-06 202 }
2016-06-06 203
2018-06-12 204 priv->rx_skbuff = kcalloc(priv->rx_ring_size,
2018-06-12 205 sizeof(*priv->rx_skbuff),
2016-06-06 206 GFP_KERNEL);
2016-06-06 207 if (!priv->rx_skbuff)
2016-07-15 208 goto free_ucc_pram;
2016-06-06 209
2018-06-12 210 priv->tx_skbuff = kcalloc(priv->tx_ring_size,
2018-06-12 211 sizeof(*priv->tx_skbuff),
2016-06-06 212 GFP_KERNEL);
2016-06-06 213 if (!priv->tx_skbuff)
2016-07-15 214 goto free_rx_skbuff;
2016-06-06 215
2016-06-06 216 priv->skb_curtx = 0;
2016-06-06 217 priv->skb_dirtytx = 0;
2016-06-06 218 priv->curtx_bd = priv->tx_bd_base;
2016-06-06 219 priv->dirty_tx = priv->tx_bd_base;
2016-06-06 220 priv->currx_bd = priv->rx_bd_base;
2016-06-06 221 priv->currx_bdnum = 0;
2016-06-06 222
2016-06-06 223 /* init parameter base */
2016-06-06 224 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
2016-06-06 225 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
2016-06-06 226 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
2016-06-06 227
2016-06-06 228 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
2016-06-06 229 qe_muram_addr(priv->ucc_pram_offset);
2016-06-06 230
2016-06-06 231 /* Zero out parameter ram */
2016-06-06 232 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
2016-06-06 233
2016-06-06 234 /* Alloc riptr, tiptr */
2016-06-06 235 riptr = qe_muram_alloc(32, 32);
Villemoes 2019-11-28 236 if (riptr < 0) {
2016-06-06 237 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
2016-06-06 238 ret = -ENOMEM;
2016-07-15 239 goto free_tx_skbuff;
2016-06-06 240 }
2016-06-06 241
2016-06-06 242 tiptr = qe_muram_alloc(32, 32);
Villemoes 2019-11-28 243 if (tiptr < 0) {
2016-06-06 244 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
2016-06-06 245 ret = -ENOMEM;
2016-07-15 246 goto free_riptr;
2016-06-06 247 }
Villemoes 2019-11-28 248 if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
Villemoes 2019-11-28 249 dev_err(priv->dev, "MURAM allocation out of addressable range\n");
Villemoes 2019-11-28 250 ret = -ENOMEM;
Villemoes 2019-11-28 251 goto free_tiptr;
Villemoes 2019-11-28 252 }
2016-06-06 253
2016-06-06 254 /* Set RIPTR, TIPTR */
2016-06-06 255 iowrite16be(riptr, &priv->ucc_pram->riptr);
2016-06-06 256 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
2016-06-06 257
2016-06-06 258 /* Set MRBLR */
2016-06-06 259 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
2016-06-06 260
2016-06-06 261 /* Set RBASE, TBASE */
2016-06-06 262 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
2016-06-06 263 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
2016-06-06 264
2016-06-06 265 /* Set RSTATE, TSTATE */
2016-06-06 266 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
2016-06-06 267 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
2016-06-06 268
2016-06-06 269 /* Set C_MASK, C_PRES for 16bit CRC */
2016-06-06 270 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
2016-06-06 271 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
2016-06-06 272
2016-06-06 273 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
2016-06-06 274 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
2016-06-06 275 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
2018-09-03 276 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
2016-06-06 277 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
2016-06-06 278 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
2016-06-06 279 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
2016-06-06 280 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
2016-06-06 281
2016-06-06 282 /* Get BD buffer */
Chamberlain 2019-01-04 283 bd_buffer = dma_alloc_coherent(priv->dev,
Chamberlain 2019-01-04 284 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
2016-06-06 285 &bd_dma_addr, GFP_KERNEL);
2016-06-06 286
2016-06-06 287 if (!bd_buffer) {
2016-06-06 288 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
2016-06-06 289 ret = -ENOMEM;
2016-07-15 290 goto free_tiptr;
2016-06-06 291 }
2016-06-06 292
2016-06-06 293 priv->rx_buffer = bd_buffer;
2016-06-06 294 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
2016-06-06 295
2016-06-06 296 priv->dma_rx_addr = bd_dma_addr;
2016-06-06 297 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
2016-06-06 298
2016-06-06 299 for (i = 0; i < RX_BD_RING_LEN; i++) {
2016-06-06 300 if (i < (RX_BD_RING_LEN - 1))
2016-06-06 301 bd_status = R_E_S | R_I_S;
2016-06-06 302 else
2016-06-06 303 bd_status = R_E_S | R_I_S | R_W_S;
2016-06-06 304
2016-06-06 @305 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
2016-06-06 306 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
2016-06-06 307 &priv->rx_bd_base[i].buf);
2016-06-06 308 }
2016-06-06 309
2016-06-06 310 for (i = 0; i < TX_BD_RING_LEN; i++) {
2016-06-06 311 if (i < (TX_BD_RING_LEN - 1))
2016-06-06 312 bd_status = T_I_S | T_TC_S;
2016-06-06 313 else
2016-06-06 314 bd_status = T_I_S | T_TC_S | T_W_S;
2016-06-06 315
2016-06-06 316 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
2016-06-06 317 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
2016-06-06 318 &priv->tx_bd_base[i].buf);
2016-06-06 319 }
2016-06-06 320
2016-06-06 321 return 0;
2016-06-06 322
2016-07-15 323 free_tiptr:
2016-06-06 324 qe_muram_free(tiptr);
2016-07-15 325 free_riptr:
2016-06-06 326 qe_muram_free(riptr);
2016-07-15 327 free_tx_skbuff:
2016-06-06 328 kfree(priv->tx_skbuff);
2016-07-15 329 free_rx_skbuff:
2016-06-06 330 kfree(priv->rx_skbuff);
2016-07-15 331 free_ucc_pram:
2016-06-06 332 qe_muram_free(priv->ucc_pram_offset);
2016-07-15 333 free_tx_bd:
2016-06-06 334 dma_free_coherent(priv->dev,
2017-05-17 335 TX_BD_RING_LEN * sizeof(struct qe_bd),
2016-06-06 336 priv->tx_bd_base, priv->dma_tx_bd);
2016-07-15 337 free_rx_bd:
2016-06-06 338 dma_free_coherent(priv->dev,
2017-05-17 339 RX_BD_RING_LEN * sizeof(struct qe_bd),
2016-06-06 340 priv->rx_bd_base, priv->dma_rx_bd);
2016-07-15 341 free_uccf:
2016-06-06 342 ucc_fast_free(priv->uccf);
2016-06-06 343
2016-06-06 344 return ret;
2016-06-06 345 }
2016-06-06 346
at line 305 was first introduced by commit
69b2fa6bdece212b48214b drivers/net: support hdlc function for QE-UCC
Qiang <qiang.zhao@xxxxxxx>
S. Miller <davem@xxxxxxxxxxxxx>
Test Service, Intel Corporation
href="https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx">https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
>.config.gz

Next message: Stefano Stabellini: "Re: [PATCH 1/2] xen/arm64: do not set SWIOTLB_NO_FORCE when swiotlb is required"
Previous message: Paul Menzel: "Re: [RESEND PATCH v2] iommu/amd: Fix extended features logging"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]