Re: [PATCH v1] clk: rockchip: Optimize PLL table memory usage

From: Heiko Stuebner
Date: Fri May 14 2021 - 08:06:09 EST


On Tue, 11 May 2021 17:07:26 +0800, Elaine@xxxxxxxxxxxxxxx wrote:
> Before the change: The sizeof rk3568_pll_rates = 2544
> Use union: The sizeof rk3568_pll_rates = 1696
>
> In future Soc, more PLL types will be added, and the
> rockchip_pll_rate_table will add more members,
> and the space savings will be even more pronounced
> by using union.

Applied, thanks!

[1/1] clk: rockchip: Optimize PLL table memory usage
commit: 23029150a05b59ebacca6dd76f6c14dc67a95877

Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>