On 5/17/2021 9:55 PM, Randy Dunlap wrote:
Hi again,
On 5/17/21 3:00 PM, Ramakrishna Saripalli wrote:
From: Ramakrishna Saripalli <rk.saripalli@xxxxxxx>...
Certain AMD processors feature a new technology called Predictive Store
Forwarding (PSF).
PSF is a micro-architectural optimization designed to improve the
performance of code execution by predicting dependencies between
loads and stores.
Incorrect PSF predictions can occur due to two reasons.
Kernel parameter predictive_store_fwd_disable has the following values
- on. Disable PSF on all CPUs.
- off. Enable PSF on all CPUs.
This is also the default setting.
Signed-off-by: Ramakrishna Saripalli<rk.saripalli@xxxxxxx>
---
.../admin-guide/kernel-parameters.txt | 5 +
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 2 +
arch/x86/include/asm/nospec-branch.h | 6 ++
arch/x86/kernel/cpu/bugs.c | 94 +++++++++++++++++++
5 files changed, 108 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 04545725f187..a5f694dccb24 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3940,6 +3940,11 @@
Format: {"off"}
Disable Hardware Transactional Memory
+ predictive_store_fwd_disable= [X86] This option controls PSF.
+ off - Turns on PSF.
+ on - Turns off PSF.
+ default : off.
and as I did earlier, I still object to "off" meaning PSF is on
and "on" meaning that PSF is off.
It's not at all user friendly.
If it's done this way because that's how the h/w bit is defined/used,
that's not a good excuse IMHO.
Hm, it sorta seems to be a common "theme" when dealing with mitigations.
And too late to fix that.
Based on previous feedback from Thomas Gleixner, I reworded this as a mitigation instead of as a "feature".
In that vein, all the mitigation code moved into bugs.c like other mitigations, similar to
spec_control_bypass_disable with an ON/OFF but no prctl/seccomp/auto.