Re: [PATCH 29/43] KVM: SVM: Tweak order of cr0/cr4/efer writes at RESET/INIT

[Reiji Watanabe]

> @@ -1204,18 +1204,13 @@ static void init_vmcb(struct kvm_vcpu *vcpu)
>         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
>         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
>
> +       svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
>         svm_set_cr4(vcpu, 0);
>         svm_set_efer(vcpu, 0);
>         save->dr6 = 0xffff0ff0;
>         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
>         vcpu->arch.regs[VCPU_REGS_RIP] = 0x0000fff0;
>
> -       /*
> -        * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
> -        * It also updates the guest-visible cr0 value.
> -        */
> -       svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);

AMD's APM Vol2 (Table 14-1 in Revision 3.37) says CR0 After INIT will be:

   CD and NW are unchanged
   Bit 4 (reserved) = 1
   All others = 0

(CR0 will be 0x60000010 after RESET)

So, it looks the CR0 value that init_vmcb() sets could be
different from what is indicated in the APM for INIT.

BTW, Intel's SDM (April 2021 version) says CR0 for Power up/Reset/INIT
will be 0x60000010 with the following note.
-------------------------------------------------
The CD and NW flags are unchanged,
bit 4 is set to 1, all other bits are cleared.
-------------------------------------------------
The note is attached as '2' to all Power up/Reset/INIT cases
looking at the SDM.  I would guess it is erroneous that
the note is attached to Power up/Reset though.

Thanks,
Reiji