Re: [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate

[Dave Hansen]

On 5/23/21 12:32 PM, Chang S. Bae wrote:
> +		/*
> +		 * Since the current task's state is safely in the XSAVE buffer, TILERELEASE
> +		 * the TILE registers to guarantee that dirty state will not interfere with the
> +		 * hardware's ability to enter the core C6 idle state.
> +		 */

Is there an architectural reason to be so specific about this one idle
state?  Are AMX and "C6 idle state" so intertwined that this comment
will age well?

I'm a bit worried that "C6 idle state" won't be meaningful to folks who
read this.

Could we maybe say:

		/*
		 * Leaving state in the TILE registers may prevent the
		 * processor from entering low-power idle states.  Use
		 * TILERELEASE to initialize the state.  Destroying
		 * fpregs state is safe after the fpstate update.
		 */

Also, referencing fpregs/fpstate is really nice because the codes
doesn't actually say "XSAVE" anywhere.

> +		if (fpu->state_mask & XFEATURE_MASK_XTILE_DATA)
> +			tile_release();

Doesn't this tile_release() need a fpregs_deactivate()?  Otherwise, the
next XRSTOR might get optimized away because it thinks there's still
good data in the fpregs.

Will this unnecessarily thwart the modified optimization in cases where
we go and run this task again without ever going out to userspace?  Will
this impact context-switch latency for *EVERY* context switch in order
to go to a lower idle state in a few minutes, hours, or never?