Re: [PATCH Part1 RFC v2 12/20] x86/compressed: Register GHCB memory when SEV-SNP is active

From: Borislav Petkov
Date: Tue May 25 2021 - 06:44:08 EST


On Fri, Apr 30, 2021 at 07:16:08AM -0500, Brijesh Singh wrote:
> diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
> index 733fca403ae5..7487d4768ef0 100644
> --- a/arch/x86/include/asm/sev-common.h
> +++ b/arch/x86/include/asm/sev-common.h
> @@ -88,6 +88,18 @@
> #define GHCB_MSR_PSC_RSVD_MASK 0xfffffULL
> #define GHCB_MSR_PSC_RESP_VAL(val) ((val) >> GHCB_MSR_PSC_ERROR_POS)
>
> +/* GHCB GPA Register */
> +#define GHCB_MSR_GPA_REG_REQ 0x012
> +#define GHCB_MSR_GPA_REG_VALUE_POS 12
> +#define GHCB_MSR_GPA_REG_VALUE_MASK 0xfffffffffffffULL

GENMASK_ULL

> +#define GHCB_MSR_GPA_REQ_VAL(v) \
> + (((v) << GHCB_MSR_GPA_REG_VALUE_POS) | GHCB_MSR_GPA_REG_REQ)
> +
> +#define GHCB_MSR_GPA_REG_RESP 0x013
> +#define GHCB_MSR_GPA_REG_RESP_VAL(v) ((v) >> GHCB_MSR_GPA_REG_VALUE_POS)
> +#define GHCB_MSR_GPA_REG_ERROR 0xfffffffffffffULL
> +#define GHCB_MSR_GPA_INVALID ~0ULL

Ditto.

> +
> /* SNP Page State Change NAE event */
> #define VMGEXIT_PSC_MAX_ENTRY 253
> #define VMGEXIT_PSC_INVALID_HEADER 0x100000001
> diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c
> index 085d3d724bc8..140c5bc07fc2 100644
> --- a/arch/x86/kernel/sev-shared.c
> +++ b/arch/x86/kernel/sev-shared.c
> @@ -81,6 +81,22 @@ static bool ghcb_get_hv_features(void)
> return true;
> }
>
> +static void snp_register_ghcb(unsigned long paddr)
> +{
> + unsigned long pfn = paddr >> PAGE_SHIFT;
> + u64 val;
> +
> + sev_es_wr_ghcb_msr(GHCB_MSR_GPA_REQ_VAL(pfn));
> + VMGEXIT();
> +
> + val = sev_es_rd_ghcb_msr();
> +
> + /* If the response GPA is not ours then abort the guest */
> + if ((GHCB_RESP_CODE(val) != GHCB_MSR_GPA_REG_RESP) ||
> + (GHCB_MSR_GPA_REG_RESP_VAL(val) != pfn))
> + sev_es_terminate(1, GHCB_TERM_REGISTER);

Nice, special termination reasons which say why the guest terminates,
cool!

:-)

--
Regards/Gruss,
Boris.

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