Re: [PATCH 1/4] ASoC: cs42l42: Fix 1536000 Bit Clock instability

[Mark Brown]

On Tue, May 25, 2021 at 10:12:39AM +0100, Richard Fitzgerald wrote:
> Reviewed-by: Richard Fitzgerald <rf@xxxxxxxxxxxxxxxxxxxxx>
> 
> On 25/05/2021 10:08, Lucas Tanure wrote:
> > The 16 Bits, 2 channels, 48K sample rate use case needs
> > to configure a safer pll_divout during the start of PLL

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