Re: [BUG] rockpro64: PCI BAR reassignment broken by commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses")

[Bjorn Helgaas]

On Tue, May 25, 2021 at 05:54:56PM +0200, Ard Biesheuvel wrote:
> On Tue, 25 May 2021 at 17:34, Peter Geis <pgwipeout@xxxxxxxxx> wrote:

> > > > >> > On 2021-05-18 10:09, Alexandru Elisei wrote:
> > > > >> >> [..]
> > > > >> >> [    0.305183] rockchip-pcie f8000000.pcie: host bridge /pcie@f8000000 ranges:
> > > > >> >> [    0.305248] rockchip-pcie f8000000.pcie:      MEM 0x00fa000000..0x00fbdfffff -> 0x00fa000000
> > > > >> >> [    0.305285] rockchip-pcie f8000000.pcie:       IO 0x00fbe00000..0x00fbefffff -> 0x00fbe00000
> > > > >> >> [    0.373705] rockchip-pcie f8000000.pcie: PCI host bridge to bus 0000:00
> > > > >> >> [    0.373730] pci_bus 0000:00: root bus resource [bus 00-1f]
> > > > >> >> [    0.373751] pci_bus 0000:00: root bus resource [mem 0xfa000000-0xfbdfffff 64bit]
> > > > >> >> [    0.373777] pci_bus 0000:00: root bus resource [io  0x0000-0xfffff] (bus address [0xfbe00000-0xfbefffff])

> ... For some reason, lspci translates the BAR values to CPU
> addresses, but the PCI side addresses are within 32-bits.

lspci shows BARs as CPU physical addresses by default.  These are the
same addresses you would see in pdev->resource[n] and the same as BAR
values you would see in dmesg.

A 64-bit CPU physical address can certainly be translated by the host
bridge to a 32-bit PCI address.  But that's not happening here because
this host bridge applies no translation (CPU physical 0xfa000000 maps
to bus address 0xfa000000).

"lspci -b" shows the PCI bus addresses.