Re: [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection

[Dietmar Eggemann]

On 26/05/2021 14:51, Beata Michalska wrote:
> On Wed, May 26, 2021 at 01:15:46PM +0100, Beata Michalska wrote:
>> On Wed, May 26, 2021 at 11:52:25AM +0200, Dietmar Eggemann wrote:
>>> On 25/05/2021 12:29, Beata Michalska wrote:
>>>> On Tue, May 25, 2021 at 10:53:07AM +0100, Valentin Schneider wrote:
>>>>> On 24/05/21 23:55, Beata Michalska wrote:
>>>>>> On Mon, May 24, 2021 at 07:01:04PM +0100, Valentin Schneider wrote:
>>>>>>> On 24/05/21 11:16, Beata Michalska wrote:

[...]

>>> BTW, how would this mechanism behave on a system with SMT and asymmetric CPU
>>> capacity? Something EAS wouldn't allow but I guess asym_cap_list will be
>>> constructed and the SD_ASYM_CPUCAPACITY_XXX flags will be set?
>> Yes, the list would get created and flags set. I do not think there is
>> a difference with current approach (?). So EAS would be disabled (it only cares
>> about SD_ASYM_CPUCAPACITY_FULL flag) but the misift might still kick in.
>>
> That depends on the arch_scale_cpu_capacity. I would imagine it would
> return SCHED_CAPACITY_SCALE for those, which means no asymmetry will
> be detected ?

I was thinking about an erroneous dts file like:

                cpu-map {
                        cluster0 {
                                core0 {
					thread0 {
                                        	cpu = <&A53_0>;
					};
					thread1 {
                                        	cpu = <&A53_1>;
					};
                                };
                                core1 {
					thread0 {
                                        	cpu = <&A53_2>;
					};
					thread1 {
                                        	cpu = <&A53_3>;
					};
                                };
                                core2 {
					thread0 {
                                        	cpu = <&A53_4>;
					};
					thread1 {
                                        	cpu = <&A53_5>;
					};
                                };
                        };

                        cluster1 {
                                core0 {
					thread0 {
                                        	cpu = <&A53_6>;
					};
					thread1 {
                                        	cpu = <&A53_7>;
					};
                                };
                        };
                };

		A53_0: cpu@0 {
			capacity-dmips-mhz = <446>;
	 	A53_1: cpu@1 {
			capacity-dmips-mhz = <1024>;
		A53_2: cpu@2 {
			capacity-dmips-mhz = <871>;
		A53_3: cpu@3 {
			capacity-dmips-mhz = <1024>;
		A53_4: cpu@4 {
			capacity-dmips-mhz = <446>;
		A53_5: cpu@5 {
			capacity-dmips-mhz = <871>;
		A53_6: cpu@6 {
			capacity-dmips-mhz = <1024>;
		A53_7: cpu@7 {
			capacity-dmips-mhz = <1024>;

Here I guess SD_ASYM_CPUCAPACITY will be attached to SMT[0-5]. So this
'capacity-dmips-mhz' config error won't be detected.

In case all CPUs (i.e. hw threads would have the correct
capacity-dmips-mhz = <1024> or not being set (default 1024))
asym_cap_list would corrcetly only have 1 entry.