Re: [RESEND PATCH V1 1/5] PCI: tegra: Fix handling BME_CHGED event

[Bjorn Helgaas]

On Thu, May 27, 2021 at 05:22:42PM +0530, Om Prakash Singh wrote:
> In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again
> APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches
> "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct.
> 
> Signed-off-by: Om Prakash Singh <omp@xxxxxxxxxx>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index bafd2c6ab3c2..c51d666c9d87 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -615,10 +615,10 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>  	struct tegra_pcie_dw *pcie = arg;
>  	struct dw_pcie_ep *ep = &pcie->pci.ep;
>  	int spurious = 1;
> -	u32 val, tmp;
> +	u32 val_l0, val, tmp;

Too bad this uses such bad variable names.  Names like "status_l0",
"status_l1", "link_status" would have avoided this in the first place.

"val" makes sense in places like config accessors where we're reading
or writing unspecified registers.  But when we're accessing specific
named registers?  Not so much.