Re: [PULL] memory: tegra: Changes for v5.14-rc1

From: Dmitry Osipenko
Date: Thu Jun 03 2021 - 15:56:34 EST

03.06.2021 17:37, Thierry Reding пишет:
> memory: tegra: Changes for v5.14-rc1
> This stable tag contains Dmitry's power domain work, including all the
> necessary dependencies from the regulator, clock and ARM SoC trees.
> ----------------------------------------------------------------
> Dmitry Osipenko (18):
> clk: tegra30: Use 300MHz for video decoder by default
> clk: tegra: Fix refcounting of gate clocks
> clk: tegra: Ensure that PLLU configuration is applied properly
> clk: tegra: Halve SCLK rate on Tegra20
> clk: tegra: Don't allow zero clock rate for PLLs
> clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
> clk: tegra: Mark external clocks as not having reset control
> clk: tegra: Don't deassert reset on enabling clocks
> regulator: core: Add regulator_sync_voltage_rdev()

> soc/tegra: regulators: Bump voltages on system reboot

This patch is a build dependency prerequisite for the "soc/tegra:
regulators: Support core domain state syncing" patch. Will you send a
new PR to Krzysztof with the remaining soc/tegra patches?