Re: [RFC PATCH v2 00/10] irqchip/irq-gic: Optimize masking by leveraging EOImode=1

[Marc Zyngier]

[+Mark, since we discussed about this on IRC]

Hi Valentin,

On Tue, 01 Jun 2021 11:25:01 +0100,
Valentin Schneider <valentin.schneider@xxxxxxx> wrote:
> 
> On 27/05/21 12:17, Marc Zyngier wrote:
> > On Tue, 25 May 2021 18:32:45 +0100,
> > Valentin Schneider <valentin.schneider@xxxxxxx> wrote:
> >> I've tested this on my Ampere eMAG, which uncovered "fun" interactions with
> >> the MSI domains. Did the same trick as the Juno with the pl011.
> >>
> >> pNMIs cause said eMAG to freeze, but that's true even without my patches. I
> >> did try them out under QEMU+KVM and that looked fine, although that means I
> >> only got to test EOImode=0. I'll try to dig into this when I get some more
> >> cycles.
> >
> > That's interesting/worrying. As far as I remember, this machine uses
> > GIC500, which is a well known quantity. If pNMIs are causing issues,
> > that'd probably be a CPU interface problem. Can you elaborate on how
> > you tried to test that part? Just using the below benchmark?
> >
> 
> Not even that, it would hang somewhere at boot. Julien suggested offline
> that it might be a problem with the secondaries' PMR initial value, but I
> really never got to do dig into it.

I just hit a similar problem on an Altra box, which seems to be
related to using PSCI for idle. PSCI has no idea about priority
masking, and enters CPU suspend with interrupt masked at the PMR
level. Good luck waking up from that.

I've pushed a test branch at [1]. It'd be really good if you could
have a quick look and let me know if that helps in your case (it
certainly does on the box I have access to).

Thanks,

	M.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=arm64/nmi-idle

-- 
Without deviation from the norm, progress is not possible.