Re: [PATCH v2 1/1] arm64: dts: mediatek: add MT6779 spi master dts node

[Mason Zhang]

On Fri, 2021-06-11 at 15:58 +0200, Matthias Brugger wrote:
> 
> On 09/04/2021 03:56, Mason Zhang wrote:
> > This patch add address-cells && size-cells in spi node based on patch v1.
> > 
> 
> Can you please come up with a better commit message, otherwise patch looks good.
> 
> Regards,
> Matthias
> 
> > Signed-off-by: Mason Zhang <Mason.Zhang@xxxxxxxxxxxx>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt6779.dtsi | 112 +++++++++++++++++++++++
> >  1 file changed, 112 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > index 370f309d32de..c81e76865d1b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> > @@ -219,6 +219,118 @@
> >  			status = "disabled";
> >  		};
> >  
> > +		spi0: spi0@1100a000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x1100a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				<&topckgen CLK_TOP_SPI>,
> > +				<&infracfg_ao CLK_INFRA_SPI0>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi1: spi1@11010000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x11010000 0 0x1000>;
> > +			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				<&topckgen CLK_TOP_SPI>,
> > +				<&infracfg_ao CLK_INFRA_SPI1>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi2: spi2@11012000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x11012000 0 0x1000>;
> > +			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				 <&topckgen CLK_TOP_SPI>,
> > +				<&infracfg_ao CLK_INFRA_SPI2>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi3: spi3@11013000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x11013000 0 0x1000>;
> > +			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				 <&topckgen CLK_TOP_SPI>,
> > +				 <&infracfg_ao CLK_INFRA_SPI3>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi4: spi4@11018000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x11018000 0 0x1000>;
> > +			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				 <&topckgen CLK_TOP_SPI>,
> > +				 <&infracfg_ao CLK_INFRA_SPI4>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi5: spi5@11019000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x11019000 0 0x1000>;
> > +			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				<&topckgen CLK_TOP_SPI>,
> > +				<&infracfg_ao CLK_INFRA_SPI5>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi6: spi6@1101d000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x1101d000 0 0x1000>;
> > +			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				 <&topckgen CLK_TOP_SPI>,
> > +				 <&infracfg_ao CLK_INFRA_SPI6>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> > +		spi7: spi7@1101e000 {
> > +			compatible = "mediatek,mt6779-spi",
> > +				     "mediatek,mt6765-spi";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			mediatek,pad-select = <0>;
> > +			reg = <0 0x1101e000 0 0x1000>;
> > +			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> > +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> > +				 <&topckgen CLK_TOP_SPI>,
> > +				 <&infracfg_ao CLK_INFRA_SPI7>;
> > +			clock-names = "parent-clk", "sel-clk", "spi-clk";
> > +		};
> > +
> >  		audio: clock-controller@11210000 {
> >  			compatible = "mediatek,mt6779-audio", "syscon";
> >  			reg = <0 0x11210000 0 0x1000>;
> > 

Dear Matthias:
	
	Thanks for your suggestions, and I have update commit message on patch
v3.Could you please help to gentle ping on patch v3 if it has no other
problems?
	Thanks a lot~

Thanks
Mason