Re: [PATCH v2 2/2] dt-bindings: clock: ad9545: Add documentation

From: kernel test robot
Date: Fri Jun 18 2021 - 00:18:42 EST

Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linux/master linus/master v5.13-rc6 next-20210617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: h8300-randconfig-s031-20210618 (attached as .config)
compiler: h8300-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/b46755cf562ff8a1a9841a4560e344099f3f054e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
git checkout b46755cf562ff8a1a9841a4560e344099f3f054e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=h8300

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>


sparse warnings: (new ones prefixed by >>)
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
>> drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] val @@ got restricted __le32 [addressable] [usertype] regval @@
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: expected unsigned int [usertype] val
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: got restricted __le32 [addressable] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: restricted __le32 degrades to integer
drivers/clk/adi/clk-ad9545.c:1407:24: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [addressable] [assigned] [usertype] regval @@ got unsigned int freq_lock_fill_rate @@
drivers/clk/adi/clk-ad9545.c:1407:24: sparse: expected restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1407:24: sparse: got unsigned int freq_lock_fill_rate
drivers/clk/adi/clk-ad9545.c:1409:88: sparse: sparse: incorrect type in argument 3 (different base types) @@ expected unsigned int val @@ got restricted __le32 [addressable] [assigned] [usertype] regval @@
drivers/clk/adi/clk-ad9545.c:1409:88: sparse: expected unsigned int val
drivers/clk/adi/clk-ad9545.c:1409:88: sparse: got restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1414:24: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [addressable] [assigned] [usertype] regval @@ got unsigned int freq_lock_drain_rate @@
drivers/clk/adi/clk-ad9545.c:1414:24: sparse: expected restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1414:24: sparse: got unsigned int freq_lock_drain_rate
drivers/clk/adi/clk-ad9545.c:1416:89: sparse: sparse: incorrect type in argument 3 (different base types) @@ expected unsigned int val @@ got restricted __le32 [addressable] [assigned] [usertype] regval @@
drivers/clk/adi/clk-ad9545.c:1416:89: sparse: expected unsigned int val
drivers/clk/adi/clk-ad9545.c:1416:89: sparse: got restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1421:24: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [addressable] [assigned] [usertype] regval @@ got unsigned int phase_lock_fill_rate @@
drivers/clk/adi/clk-ad9545.c:1421:24: sparse: expected restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1421:24: sparse: got unsigned int phase_lock_fill_rate
drivers/clk/adi/clk-ad9545.c:1423:89: sparse: sparse: incorrect type in argument 3 (different base types) @@ expected unsigned int val @@ got restricted __le32 [addressable] [assigned] [usertype] regval @@
drivers/clk/adi/clk-ad9545.c:1423:89: sparse: expected unsigned int val
drivers/clk/adi/clk-ad9545.c:1423:89: sparse: got restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1428:24: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [addressable] [assigned] [usertype] regval @@ got unsigned int phase_lock_drain_rate @@
drivers/clk/adi/clk-ad9545.c:1428:24: sparse: expected restricted __le32 [addressable] [assigned] [usertype] regval
drivers/clk/adi/clk-ad9545.c:1428:24: sparse: got unsigned int phase_lock_drain_rate
drivers/clk/adi/clk-ad9545.c:1430:90: sparse: sparse: incorrect type in argument 3 (different base types) @@ expected unsigned int val @@ got restricted __le32 [addressable] [assigned] [usertype] regval @@
drivers/clk/adi/clk-ad9545.c:1430:90: sparse: expected unsigned int val
drivers/clk/adi/clk-ad9545.c:1430:90: sparse: got restricted __le32 [addressable] [assigned] [usertype] regval

vim +1114 drivers/clk/adi/clk-ad9545.c

f88d17c990b731 Alexandru Tachici 2021-06-14 1089
f88d17c990b731 Alexandru Tachici 2021-06-14 1090 static int ad9545_out_clk_get_phase(struct clk_hw *hw)
f88d17c990b731 Alexandru Tachici 2021-06-14 1091 {
f88d17c990b731 Alexandru Tachici 2021-06-14 1092 struct ad9545_out_clk *clk = to_out_clk(hw);
f88d17c990b731 Alexandru Tachici 2021-06-14 1093 u64 input_edges_nr;
f88d17c990b731 Alexandru Tachici 2021-06-14 1094 u64 phase_code;
f88d17c990b731 Alexandru Tachici 2021-06-14 1095 __le32 regval;
f88d17c990b731 Alexandru Tachici 2021-06-14 1096 u32 phase_conf;
f88d17c990b731 Alexandru Tachici 2021-06-14 1097 u32 qdiv;
f88d17c990b731 Alexandru Tachici 2021-06-14 1098 int ret;
f88d17c990b731 Alexandru Tachici 2021-06-14 1099
f88d17c990b731 Alexandru Tachici 2021-06-14 1100 ret = ad9545_get_q_div(clk->st, clk->address, &qdiv);
f88d17c990b731 Alexandru Tachici 2021-06-14 1101 if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14 1102 return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14 1103
f88d17c990b731 Alexandru Tachici 2021-06-14 1104 ret = regmap_read(clk->st->regmap, AD9545_QX_PHASE_CONF(clk->address), &phase_conf);
f88d17c990b731 Alexandru Tachici 2021-06-14 1105 if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14 1106 return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14 1107
f88d17c990b731 Alexandru Tachici 2021-06-14 1108 ret = regmap_bulk_read(clk->st->regmap, AD9545_QX_PHASE(clk->address), &regval, 4);
f88d17c990b731 Alexandru Tachici 2021-06-14 1109 if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14 1110 return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14 1111
f88d17c990b731 Alexandru Tachici 2021-06-14 1112 /* Qxy phase bitfield is 33 bits long, with last bit in PHASE_CONF reg */
f88d17c990b731 Alexandru Tachici 2021-06-14 1113 phase_code = !!(phase_conf & AD9545_QX_PHASE_32_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14 @1114 phase_code = (phase_code >> 32) + cpu_to_le32(regval);
f88d17c990b731 Alexandru Tachici 2021-06-14 1115
f88d17c990b731 Alexandru Tachici 2021-06-14 1116 input_edges_nr = 2 * qdiv + !!(phase_conf & AD9545_QX_HALF_DIV_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14 1117
f88d17c990b731 Alexandru Tachici 2021-06-14 1118 /*
f88d17c990b731 Alexandru Tachici 2021-06-14 1119 * phase = 360 * (Qxy Phase / E) where:
f88d17c990b731 Alexandru Tachici 2021-06-14 1120 * E is the total number of input edges per output period of the Q-divider.
f88d17c990b731 Alexandru Tachici 2021-06-14 1121 */
f88d17c990b731 Alexandru Tachici 2021-06-14 1122 return div64_u64(phase_code * 360, input_edges_nr);
f88d17c990b731 Alexandru Tachici 2021-06-14 1123 }
f88d17c990b731 Alexandru Tachici 2021-06-14 1124

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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip