Re: [PATCH] arm64: PCI: Enable SMC conduit

[Jason Gunthorpe]

On Sat, Jun 19, 2021 at 12:34:57PM -0400, Jon Masters wrote:
> Hi Jason,
> 
> On Fri, Jun 18, 2021 at 10:06 AM Jason Gunthorpe <jgg@xxxxxxxxxx> wrote:
> >
> > On Fri, Jun 18, 2021 at 09:21:54AM -0400, Jon Masters wrote:
> > >    Hi Jason,
> > >    On Wed, Jun 16, 2021 at 1:38 PM Jason Gunthorpe <[1]jgg@xxxxxxxxxx>
> > >    wrote:
> > >
> > >      On Thu, Mar 25, 2021 at 01:12:31PM +0000, Lorenzo Pieralisi wrote:
> > >      However, in modern server type systems the PCI config space is often
> > >      a
> > >      software fiction being created by firmware throughout the PCI
> > >      space. This has become necessary as the config space has exploded in
> > >      size and complexity and PCI devices themselves have become very,
> > >      very
> > >      complicated. Not just the config space of single devices, but even
> > >      bridges and topology are SW created in some cases.
> > >      HW that is doing this is already trapping the config cycles somehow,
> > >      presumably with some very ugly way like x86's SMM. Allowing a
> > >      designed
> > >      in way to inject software into the config space cycles does sound a
> > >      lot cleaner and better to me.
> > >
> > >    This is not required. SMM is terrible, indeed. But we don't have to
> > >    relive it in Arm just because that's [EL3] the easy place to shove
> > >    things :)
> >
> > "This is not required"? What does that mean?
> 
> It's not required to implement platform hacks in SMM-like EL3. The
> correct place to do this kind of thing is behind the scenes in a
> platform microcontroller (note that I do not necessarily mean Arm's
> SCP approach, you can do much better than that).

This is what some are doing, but burning that much sillicon area just
to run the non-performance software for PCI config space feels really
extreme to me - and basically means most of the the mid tier won't do
it.

Let alone the complicated questions around how to manage this other
processor, do in-field upgrades, deal with it crashing, and its
debugging/etc.

> > AFAIK x86 has HW that traps the read/writes to the ECAM and can
> > trigger a FW flow to emulate them, maybe in SMM, I don't know the
> > details. It ceratinly used to be like this when SMM could trap the
> > config space io read/write registers.
> 
> They trap to something that isn't in SMM, but it is in firmware. That
> is the correct (in my opinion) approach to this. It's one time where
> I'm going to say that all the Arm vendors should be doing what Intel
> is doing in their implementation today.

What is the ARM equivilant to "not in SMM but it is in firmware" ?

> > Is that what you want to see for ARM? Is that better than a SMC?
> 
> Yes, because you preserve perfect ECAM semantics and correct it behind
> the scenes. That's what people should be building.

I'm not really talking about perfect ECAM semantics here, but the
whole ball of wax - the endless rabbit hole of a SOC that has 10 "pci
devices" on chip and has 40kb of config space that needs to be
presented to the OS. How do you do that in a silicon efficient way?
How do you deal with it in a way that allows contigencies when the HW
is inevitably wrong?

The usual answer is to use a lot of software and run it someplace.

> > That is alot of special magic hardware to avoid a SMC call...
> 
> And it's the correct way to do it. Either that, or get ECAM perfect up
> front and do pre-si testing under emulation to confirm.

This is what the sophisticated people are doing - but I think
insisting on it leaves out the middle of the market that can't afford
the silicon area for extra microcontrollers, afford the extra design
time to do all the needed high fidelity emulation to be sure it is
right, or afford a mask respin.

Again, it is not just ECAM, the bad root complex's are a really tragic
dysfunction in the IP marketplace. Even if they were perfect we'd
still want to have SW injected in config cycles, some how..

Jason