Re: [Patch v2 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh

[Thara Gopinath]

On 6/24/21 1:48 PM, Matthias Kaehlcke wrote:
> On Thu, Jun 24, 2021 at 07:58:09AM -0400, Thara Gopinath wrote:
> > Introduce SCM calls to access/configure limits management hardware(LMH).
> >
> > Signed-off-by: Thara Gopinath <thara.gopinath@xxxxxxxxxx>
> > ---
> >
> > v1->v2:
> > 	Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and
> > 	payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review
> > 	comments.
> >
> >   drivers/firmware/qcom_scm.c | 54 +++++++++++++++++++++++++++++++++++++
> >   drivers/firmware/qcom_scm.h |  4 +++
> >   include/linux/qcom_scm.h    | 14 ++++++++++
> >   3 files changed, 72 insertions(+)
> >
> > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> > index ee9cb545e73b..19e9fb91d084 100644
> > --- a/drivers/firmware/qcom_scm.c
> > +++ b/drivers/firmware/qcom_scm.c
> > @@ -1147,6 +1147,60 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
> >   }
> >   EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
> >   
> > +bool qcom_scm_lmh_dcvsh_available(void)
> > +{
> > +	return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
> > +}
> > +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
> > +
> > +int qcom_scm_lmh_profile_change(u32 profile_id)
> > +{
> > +	struct qcom_scm_desc desc = {
> > +		.svc = QCOM_SCM_SVC_LMH,
> > +		.cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE,
> > +		.arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
> > +		.args[0] = profile_id,
> > +		.owner = ARM_SMCCC_OWNER_SIP,
> > +	};
> > +
> > +	return qcom_scm_call(__scm->dev, &desc, NULL);
> > +}
> > +EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
> > +
> > +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
> > +		       u64 limit_node, u32 node_id, u64 version)
> > +{
> > +	dma_addr_t payload_phys;
> > +	u32 *payload_buf;
> > +	int payload_size = 5 * sizeof(u32);
> > +
> > +	struct qcom_scm_desc desc = {
> > +		.svc = QCOM_SCM_SVC_LMH,
> > +		.cmd = QCOM_SCM_LMH_LIMIT_DCVSH,
> > +		.arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL,
> > +					QCOM_SCM_VAL, QCOM_SCM_VAL),
> > +		.args[1] = payload_size,
> > +		.args[2] = limit_node,
> > +		.args[3] = node_id,
> > +		.args[4] = version,
> > +		.owner = ARM_SMCCC_OWNER_SIP,
> > +	};
> > +
> > +	payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL);
> > +	if (!payload_buf)
> > +		return -ENOMEM;
> > +
> > +	payload_buf[0] = payload_fn;
> > +	payload_buf[1] = 0;
> > +	payload_buf[2] = payload_reg;
> > +	payload_buf[3] = 1;
> > +	payload_buf[4] = payload_val;
> > +
> > +	desc.args[0] = payload_phys;
> > +	return qcom_scm_call(__scm->dev, &desc, NULL);
>
> dma_free_coherent()?

yep.. A free should be done here. Will fix it

>

--
Warm Regards
Thara (She/Her/Hers)