[PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations
From: Apurva Nandan
Date: Tue Jul 13 2021 - 08:57:52 EST
Hi,
This series proposes fixes for cadence-quadspi controller for the
following issues with SPI NAND flashes:
- Due to auto-HW polling without address phase, the cadence-quadspi
controller timeouts when performing any write operation on SPI NAND
flash.
- When checking for DTR spi_mem_op, cadence-quadspi doesn't ignore a
zero length phase in the SPI instruction, resulting in false negatives.
This series has been tested on TI J721e EVM with the Winbond W35N01JW
flash.
Apurva Nandan (2):
spi: cadence-quadspi: Disable Auto-HW polling
spi: cadence-quadspi: Fix check condition for DTR ops
drivers/spi/spi-cadence-quadspi.c | 39 ++++++++++++++++++-------------
1 file changed, 23 insertions(+), 16 deletions(-)
--
2.17.1