Re: [PATCH v5 2/8] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

From: Rob Herring
Date: Tue Jul 13 2021 - 22:26:57 EST


On Tue, Jul 13, 2021 at 08:28:35AM +0200, Mauro Carvalho Chehab wrote:
> Document the bindings for HiKey 970 (hi3670) PCIe PHY
> interface, supported via the pcie-kirin driver.

Same comments on this one.

>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
> ---
> .../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
> new file mode 100644
> index 000000000000..976ab6fe7b0a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HiSilicon Kirin970 PCIe PHY
> +
> +maintainers:
> + - Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
> +
> +description: |+
> + Bindings for PCIe PHY on HiSilicon Kirin 970.
> +
> +properties:
> + compatible:
> + const: hisilicon,hi970-pcie-phy
> +
> + "#phy-cells":
> + const: 0
> +
> + reg:
> + maxItems: 1
> + description: PHY Control registers
> +
> + reg-names:
> + const: phy
> +
> + phy-supply:
> + description: The PCIe PHY power supply
> +
> + clocks:
> + items:
> + - description: PCIe PHY clock
> + - description: PCIe AUX clock
> + - description: PCIe APB PHY clock
> + - description: PCIe APB SYS clock
> + - description: PCIe ACLK clock
> +
> + clock-names:
> + items:
> + - const: pcie_phy_ref
> + - const: pcie_aux
> + - const: pcie_apb_phy
> + - const: pcie_apb_sys
> + - const: pcie_aclk
> +
> + reset-gpios:
> + description: PCI PERST reset GPIOs
> + maxItems: 4

Hiding the 4 ports in the phy?

> +
> + clkreq-gpios:
> + description: Clock request GPIOs
> + maxItems: 3
> +
> + hisilicon,eye-diagram-param:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Eye diagram for phy.

Is there a size to this array?

> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - reset-gpios
> + - clkreq-gpios
> + - hisilicon,eye-diagram-param
> + - phy-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/hi3670-clock.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + pcie_phy: pcie-phy@fc000000 {
> + compatible = "hisilicon,hi970-pcie-phy";
> + reg = <0x0 0xfc000000 0x0 0x80000>;
> + reg-names = "phy";
> + #phy-cells = <0>;
> + phy-supply = <&ldo33>;
> + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
> + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
> + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
> + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
> + <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
> + clock-names = "pcie_phy_ref", "pcie_aux",
> + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
> + <&gpio3 1 0 >, <&gpio27 4 0 >;
> + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >;
> + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF
> + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>;
> + };
> + };
> +...
> --
> 2.31.1
>
>