Re: [PATCH v4 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer

[Andy Shevchenko]

On Wed, Jul 14, 2021 at 08:07:44AM -0600, Rob Herring wrote:
> On Wed, Jul 14, 2021 at 3:04 AM Andy Shevchenko
> <andriy.shevchenko@xxxxxxxxxxxxxxx> wrote:
> > On Tue, Jul 13, 2021 at 08:47:56PM -0600, Rob Herring wrote:
> > > On Mon, Jun 28, 2021 at 11:44:09AM +0530, shruthi.sanil@xxxxxxxxx wrote:
> >
> > > > +  The parent node represents the common general configuration details and
> > > > +  the child nodes represents the counter and timers.
> > >
> > > I don't think all the child nodes are necessary. Are the counters and
> > > timers configurable (say on another SoC)? If not, then a single node
> > > here would suffice.
> >
> > If you may notice the children may have different properties that can't be
> > known ahead, such as IRQ line. On some platforms it may be this mapping, on
> > another it maybe different.
> 
> What I noticed is it's all the same clock and 1 interrupt for each
> timer can be just a single 'interrupts' property with 8 entries.

This may work.

> Is there a platform that's different or that's a hypothetical? Because
> hypothetically, every aspect of every IP could change. But we don't
> try to parameterize everything in DT. It's a judgement call between
> implying things from compatible and explicit DT properties.
> 
> > With all respect for the simplification I think we can't do it here.
> 
> You can. Any data in DT could be in the kernel. It's a question of
> balance, not can or can't.

Not only, it's also matters of what exactly hardware is: 8 timers or timer with
8 channels. If it's the former one, I prefer to have DT exactly like originally
suggested, otherwise I will agree on your proposal.

-- 
With Best Regards,
Andy Shevchenko