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It appears that some code lines raise the question why they are needed

and how they are participated in the calculus of the resulting values.

Document this in a form of the top comment in the module file.

Reported-by: Liu Ying <victor.liu@xxxxxxx>

Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>

---

v2: renamed variables in formulas to follow the code, added floor()

drivers/clk/clk-fractional-divider.c | 34 +++++++++++++++++++++++++++-

1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c

index 5f4b6a8aef67..7f7f688f8de5 100644

--- a/drivers/clk/clk-fractional-divider.c

+++ b/drivers/clk/clk-fractional-divider.c

@@ -3,8 +3,38 @@

* Copyright (C) 2014 Intel Corporation

*

* Adjustable fractional divider clock implementation.

- * Output rate = (m / n) * parent_rate.

* Uses rational best approximation algorithm.

+ *

+ * Output is calculated as

+ *

+ * rate = (m / n) * parent_rate (1)

+ *

+ * This is useful when on die we have a prescaler block which asks for

+ * m (numerator) and n (denominator) values to be provided to satisfy

+ * the (1) as much as possible.

+ *

+ * Since m and n have the limitation by a range, e.g.

+ *

+ * n >= 1, n < N_width, where N_width = 2^nwidth (2)

+ *

+ * for some cases the output may be saturated. Hence, from (1) and (2),

+ * assuming the worst case when m = 1, the inequality

+ *

+ * floor(log2(parent_rate / rate)) <= nwidth (3)

+ *

+ * may be derived. Thus, in cases when

+ *

+ * (parent_rate / rate) >> N_width (4)

+ *

+ * we scale up the rate by 2^scale, where

+ *

+ * scale = floor(log2(parent_rate / rate)) - nwidth (5)

+ *

+ * and assume that the IP, that needs m and n, has also its own

+ * prescaler, which is capable to divide by 2^scale. In this way

+ * we get the denominator to satisfy the desired range (2) and

+ * at the same time much much better result of m and n than simple

+ * saturated values.

*/

#include <linux/clk-provider.h>

@@ -81,6 +111,8 @@ void clk_fractional_divider_general_approximation(struct clk_hw *hw,

* Get rate closer to *parent_rate to guarantee there is no overflow

* for m and n. In the result it will be the nearest rate left shifted

* by (scale - fd->nwidth) bits.

+ *

+ * For the detailed explanation see the top comment in this file.

*/

if (!(fd->flags & CLK_FRAC_DIVIDER_NO_PRESCALER)) {

unsigned long scale = fls_long(*parent_rate / rate - 1);

--

2.30.2

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