[tglx-devel:irq/msi 4/8] drivers/pci/msi.c:316:12: warning: passing argument 1 of 'readl' makes pointer from integer without a cast

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git irq/msi
head:   148a9616eb053a8c0d0c9859fde99fa2aee3ccea
commit: abefd748ab60997c05fcd79e7b4072cd4fd47c19 [4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible
config: i386-randconfig-r034-20210720 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
reproduce (this is a W=1 build):
        # https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/commit/?id=abefd748ab60997c05fcd79e7b4072cd4fd47c19
        git remote add tglx-devel https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
        git fetch --no-tags tglx-devel irq/msi
        git checkout abefd748ab60997c05fcd79e7b4072cd4fd47c19
        # save the attached .config to linux build tree
        make W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

   drivers/pci/msi.c: In function '__pci_write_msi_msg':
>> drivers/pci/msi.c:316:12: warning: passing argument 1 of 'readl' makes pointer from integer without a cast [-Wint-conversion]
     316 |   readl(msg->data, base + PCI_MSIX_ENTRY_DATA);
         |         ~~~^~~~~~
         |            |
         |            u32 {aka unsigned int}
   In file included from include/linux/io.h:13,
                    from include/linux/irq.h:20,
                    from drivers/pci/msi.c:12:
   arch/x86/include/asm/io.h:48:54: note: expected 'const volatile void *' but argument is of type 'u32' {aka 'unsigned int'}
      48 | static inline type name(const volatile void __iomem *addr) \
         |                         ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
   arch/x86/include/asm/io.h:59:1: note: in expansion of macro 'build_mmio_read'
      59 | build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
         | ^~~~~~~~~~~~~~~
   arch/x86/include/asm/io.h:75:15: error: too many arguments to function 'readl'
      75 | #define readl readl
         |               ^~~~~
   drivers/pci/msi.c:316:3: note: in expansion of macro 'readl'
     316 |   readl(msg->data, base + PCI_MSIX_ENTRY_DATA);
         |   ^~~~~
   arch/x86/include/asm/io.h:59:17: note: declared here
      59 | build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
         |                 ^~~~~
   arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
      48 | static inline type name(const volatile void __iomem *addr) \
         |                    ^~~~


vim +/readl +316 drivers/pci/msi.c

   283	
   284	void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
   285	{
   286		struct pci_dev *dev = msi_desc_to_pci_dev(entry);
   287	
   288		if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
   289			/* Don't touch the hardware now */
   290		} else if (entry->msi_attrib.is_msix) {
   291			void __iomem *base = pci_msix_desc_addr(entry);
   292			bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
   293	
   294			if (!base)
   295				goto skip;
   296	
   297			/*
   298			 * The specification mandates that the entry is masked
   299			 * when the message is modified:
   300			 *
   301			 * "If software changes the Address or Data value of an
   302			 * entry while the entry is unmasked, the result is
   303			 * undefined."
   304			 */
   305			if (unmasked)
   306				__pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
   307	
   308			writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
   309			writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
   310			writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
   311	
   312			if (unmasked)
   313				__pci_msix_desc_mask_irq(entry, 0);
   314	
   315			/* Ensure that the writes are visible in the device */
 > 316			readl(msg->data, base + PCI_MSIX_ENTRY_DATA);
   317		} else {
   318			int pos = dev->msi_cap;
   319			u16 msgctl;
   320	
   321			pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
   322			msgctl &= ~PCI_MSI_FLAGS_QSIZE;
   323			msgctl |= entry->msi_attrib.multiple << 4;
   324			pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
   325	
   326			pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
   327					       msg->address_lo);
   328			if (entry->msi_attrib.is_64) {
   329				pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
   330						       msg->address_hi);
   331				pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
   332						      msg->data);
   333			} else {
   334				pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
   335						      msg->data);
   336			}
   337			/* Ensure that the writes are visible in the device */
   338			pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
   339		}
   340	
   341	skip:
   342		entry->msg = *msg;
   343	
   344		if (entry->write_msi_msg)
   345			entry->write_msi_msg(entry, entry->write_msi_msg_data);
   346	

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