Re: [PATCH net 1/1] net: dsa: qca: ar9331: reorder MDIO write sequence

[Florian Fainelli]

On 8/2/2021 11:37 PM, Oleksij Rempel wrote:
> In case of this switch we work with 32bit registers on top of 16bit
> bus. Some registers (for example access to forwarding database) have
> trigger bit on the first 16bit half of request and the result +
> configuration of request in the second half. Without this patch, we would
> trigger database operation and overwrite result in one run.
>
> To make it work properly, we should do the second part of transfer
> before the first one is done.
>
> So far, this rule seems to work for all registers on this switch.
>
> Fixes: ec6698c272de ("net: dsa: add support for Atheros AR9331 built-in switch")
> Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
> Reviewed-by: Andrew Lunn <andrew@xxxxxxx>

Reviewed-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
--
Florian