Re: [PATCH 3/3] soc: mediatek: mmsys: add MT8365 support

[Matthias Brugger]

Hi Fabien,

On 19/05/2021 18:18, Fabien Parent wrote:
> Add DSI mmsys connections for the MT8365 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>
> ---
>  drivers/soc/mediatek/mt8365-mmsys.h | 60 +++++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c    | 11 ++++++
>  2 files changed, 71 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8365-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> new file mode 100644
> index 000000000000..2475aeb79791
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -0,0 +1,60 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
> +#define __SOC_MEDIATEK_MT8365_MMSYS_H
> +
> +#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c
> +#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54
> +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60
> +#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64
> +#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68
> +
> +#define MT8365_RDMA0_SOUT_COLOR0			0x1
> +#define MT8365_DITHER_MOUT_EN_DSI0			0x1
> +#define MT8365_DSI0_SEL_IN_DITHER			0x1
> +#define MT8365_RDMA0_SEL_IN_OVL0			0x0
> +#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0
> +#define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0
> +#define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)
> +
> +static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
> +		MT8365_OVL0_MOUT_PATH0_SEL

I pushed this patch to v4.15-next/soc
As we now include the mask field in mtk_mmsys_routes I updated that in the patch.
Please let me know if I screwed something up.

Regards,
Matthias

> +	},
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
> +		MT8365_RDMA0_SEL_IN_OVL0
> +	},
> +	{
> +		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> +		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
> +		MT8365_RDMA0_SOUT_COLOR0
> +	},
> +	{
> +		DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
> +		MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
> +		MT8365_DISP_COLOR_SEL_IN_COLOR0
> +	},
> +	{
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> +		MT8365_DITHER_MOUT_EN_DSI0
> +	},
> +	{
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> +		MT8365_DSI0_SEL_IN_DITHER
> +	},
> +	{
> +		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> +		MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
> +		MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
> +	},
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..44aff822d035 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -13,6 +13,7 @@
>  #include "mtk-mmsys.h"
>  #include "mt8167-mmsys.h"
>  #include "mt8183-mmsys.h"
> +#include "mt8365-mmsys.h"
>  
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>  	.clk_driver = "clk-mt2701-mm",
> @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>  	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
>  };
>  
> +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> +	.clk_driver = "clk-mt8365-mm",
> +	.routes = mt8365_mmsys_routing_table,
> +	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> +};
> +
>  struct mtk_mmsys {
>  	void __iomem *regs;
>  	const struct mtk_mmsys_driver_data *data;
> @@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>  		.compatible = "mediatek,mt8183-mmsys",
>  		.data = &mt8183_mmsys_driver_data,
>  	},
> +	{
> +		.compatible = "mediatek,mt8365-mmsys",
> +		.data = &mt8365_mmsys_driver_data,
> +	},
>  	{ }
>  };
>  
>