Re: [RFC] bitops/non-atomic: make @nr unsigned to avoid any DIV

[Vineet Gupta]

On 8/6/21 6:42 AM, Will Deacon wrote:
> On Thu, Aug 05, 2021 at 12:14:08PM -0700, Vineet Gupta wrote:
>> signed math causes generation of costlier instructions such as DIV when
>> they could be done by barrerl shifter.
>>
>> Worse part is this is not caught by things like bloat-o-meter since
>> instruction length / symbols are typically same size.
>>
>> e.g.
>>
>> stock (signed math)
>> __________________
>>
>> 919b4614 <test_taint>:
>> 919b4614:	div	r2,r0,0x20
>>                  ^^^
>> 919b4618:	add2	r2,0x920f6050,r2
>> 919b4620:	ld_s	r2,[r2,0]
>> 919b4622:	lsr	r0,r2,r0
>> 919b4626:	j_s.d	[blink]
>> 919b4628:	bmsk_s	r0,r0,0
>> 919b462a:	nop_s
>>
>> (patched) unsigned math
>> __________________
>>
>> 919b4614 <test_taint>:
>> 919b4614:	lsr	r2,r0,0x5  @nr/32
>>                  ^^^
>> 919b4618:	add2	r2,0x920f6050,r2
>> 919b4620:	ld_s	r2,[r2,0]
>> 919b4622:	lsr	r0,r2,r0     #test_bit()
>> 919b4626:	j_s.d	[blink]
>> 919b4628:	bmsk_s	r0,r0,0
>> 919b462a:	nop_s
> Just FYI, but on arm64 the existing codegen is alright as we have both
> arithmetic and logical shifts.

ARC does too: There's LSR (Logical shift right) and ASR (Arithmetic 
Shift Right).
So perhaps something to be done in the compiler.

>> Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxxxx>
>> ---
>> This is an RFC for feeback, I understand this impacts every arch,
>> but as of now it is only buld/run tested on ARC.
>> ---
>> ---
>>   include/asm-generic/bitops/non-atomic.h | 14 +++++++-------
>>   1 file changed, 7 insertions(+), 7 deletions(-)
> Acked-by: Will Deacon <will@xxxxxxxxxx>
>
> We should really move test_bit() into the atomic header, but I failed to fix
> the resulting include mess last time I tried that.

OK I'll give it a try too.