On Sat, 7 Aug 2021 22:55:37 +0800thanks for the reply,
Xianting Tian <xianting.tian@xxxxxxxxxxxxxxxxx> wrote:
Introduce ARCH_DMA_MINALIGN to riscv arch.It's not a good idea to blindly set this for all riscv. For "coherent"
Signed-off-by: Xianting Tian <xianting.tian@xxxxxxxxxxxxxxxxx>
---
arch/riscv/include/asm/cache.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 9b58b1045..2945bbe2b 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -11,6 +11,8 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
platforms, this is not necessary and will waste memory.
+
/*
* RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
* the flat loader aligns it accordingly.