Re: [PATCH 04/39] arm64: dts: qcom: sdm630: Add interconnect provider nodes

[Dmitry Baryshkov]

On 29/07/2021 01:25, Konrad Dybcio wrote:
> Add interconnect provider nodes to allow for NoC bus scaling.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
> ---
>   arch/arm64/boot/dts/qcom/sdm630.dtsi | 59 ++++++++++++++++++++++++++++
>   1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index e2cbe210048e..c46b7327afbe 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -4,6 +4,7 @@
>    */
>   
>   #include <dt-bindings/clock/qcom,gcc-sdm660.h>
> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
>   #include <dt-bindings/clock/qcom,rpmcc.h>
>   #include <dt-bindings/power/qcom-rpmpd.h>
>   #include <dt-bindings/gpio/gpio.h>
> @@ -516,11 +517,38 @@ rng: rng@793000 {
>   			clock-names = "core";
>   		};
>   
> +		bimc: interconnect@1008000 {
> +			compatible = "qcom,sdm660-bimc";
> +			reg = <0x01008000 0x78000>;
+			#interconnect-cells = <1>;
> +			clock-names = "bus", "bus_a";
> +			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
> +				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
> +		};
> +
>   		restart@10ac000 {
>   			compatible = "qcom,pshold";
>   			reg = <0x010ac000 0x4>;
>   		};
>   
> +		cnoc: interconnect@1500000 {
> +			compatible = "qcom,sdm660-cnoc";
> +			reg = <0x01500000 0x10000>;
> +			#interconnect-cells = <1>;
> +			clock-names = "bus", "bus_a";
> +			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
> +				 <&rpmcc RPM_SMD_CNOC_A_CLK>;
> +		};
> +
> +		snoc: interconnect@1626000 {
> +			compatible = "qcom,sdm660-snoc";
> +			reg = <0x01626000 0x7090>;
> +			#interconnect-cells = <1>;
> +			clock-names = "bus", "bus_a";
> +			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
> +				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
> +		};

Interesting, this disagrees with the downstream dts. It looks like you 
are including offset to QoS registers into start address. Although we do 
not use other registers from the NoC, I think it would be better to use 
correct device address and adjust register offset in the interconnect 
driver.

> +
>   		anoc2_smmu: iommu@16c0000 {
>   			compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
>   			reg = <0x016c0000 0x40000>;
> @@ -564,6 +592,25 @@ anoc2_smmu: iommu@16c0000 {
>   			status = "disabled";
>   		};
>   
> +		a2noc: interconnect@1704000 {
> +			compatible = "qcom,sdm660-a2noc";
> +			reg = <0x01704000 0xc100>;
> +			#interconnect-cells = <1>;
> +			clock-names = "bus", "bus_a";
> +			clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
> +				 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
> +		};
> +
> +		mnoc: interconnect@1745000 {
> +			compatible = "qcom,sdm660-mnoc";
> +			reg = <0x01745000 0xA010>;
> +			#interconnect-cells = <1>;
> +			clock-names = "bus", "bus_a", "iface";
> +			clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
> +				 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
> +				 <&mmcc AHB_CLK_SRC>;
> +		};
> +
>   		tcsr_mutex_regs: syscon@1f40000 {
>   			compatible = "syscon";
>   			reg = <0x01f40000 0x20000>;
> @@ -1156,6 +1203,18 @@ mmss_smmu: iommu@cd00000 {
>   			status = "disabled";
>   		};
>   
> +		gnoc: interconnect@17900000 {
> +			compatible = "qcom,sdm660-gnoc";
> +			reg = <0x17900000 0xe000>;
> +			#interconnect-cells = <1>;
> +			/*
> +			 * This one apparently features no clocks,
> +			 * so let's not mess with the driver needlessly
> +			 */
> +			clock-names = "bus", "bus_a";
> +			clocks = <&xo_board>, <&xo_board>;
> +		};
> +
>   		apcs_glb: mailbox@17911000 {
>   			compatible = "qcom,sdm660-apcs-hmss-global";
>   			reg = <0x17911000 0x1000>;


--
With best wishes
Dmitry