[PATCH 14/18] ARC: mm: hack to allow 2 level build with 4 level code
From: Vineet Gupta
Date: Tue Aug 10 2021 - 20:43:48 EST
PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-*
but only for !__ASSEMBLY__
tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs
for CONFIG_PGTABLE_LEVEL={2,3} and works for 4.
So add a workaround local to tlbex.S - the proper fix is to change
asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too
Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxx>
---
arch/arc/mm/tlbex.S | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 6b5872197005..d08bd09a0afc 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -145,6 +145,14 @@ ex_saved_reg1:
;TLB Miss handling Code
;============================================================================
+#ifndef PMD_SHIFT
+#define PMD_SHIFT PUD_SHIFT
+#endif
+
+#ifndef PUD_SHIFT
+#define PUD_SHIFT PGDIR_SHIFT
+#endif
+
;-----------------------------------------------------------------------------
; This macro does the page-table lookup for the faulting address.
; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
--
2.25.1