Re: [PING][PATCH V9 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS

[Like Xu]

Hi Paolo,

On 28/7/2021 11:45 pm, Peter Zijlstra wrote:
> > Like Xu (17):
> >    perf/core: Use static_call to optimize perf_guest_info_callbacks
> >    perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server
> >    perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest
> >    perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values
> >    KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled
> >    KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter
> >    KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS
> >    KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter
> >    KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter
> >    KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS
> >    KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS
> >    KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled
> >    KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h
> >    KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations
> >    KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability
> >    KVM: x86/cpuid: Refactor host/guest CPU model consistency check
> >    KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64
> >
> > Peter Zijlstra (Intel) (1):
> >    x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value
> Looks good:
>
> Acked-by: Peter Zijlstra (Intel)<peterz@xxxxxxxxxxxxx>
>
> How do we want to route this, all through the KVM tree?

Do you have any comments for the latest version[1]
or do we have a chance to get it queued for mainline ?

I would really like to ease the burden of Lingshan on
maintaining this feature and on the basis of this work,
the guest BTS (Branch Tracking Store) is also ready to go.

Thanks,
Like Xu

[1] https://lore.kernel.org/kvm/20210806133802.3528-1-lingshan.zhu@xxxxxxxxx/