[PATCH v13 4/6] arm: dts: rockchip: Add SFC to RV1108

From: Jon Lin
Date: Thu Aug 12 2021 - 09:46:23 EST


From: Chris Morgan <macromorgan@xxxxxxxxxxx>

Add a devicetree entry for the Rockchip SFC for the RV1108 SOC.

Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx>
Signed-off-by: Jon Lin <jon.lin@xxxxxxxxxxxxxx>
---

Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None

arch/arm/boot/dts/rv1108.dtsi | 37 +++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 9bd0acf3b708..6ec9b25a9e0a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -536,6 +536,17 @@
status = "disabled";
};

+ sfc: spi@301c0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x301c0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
gmac: eth@30200000 {
compatible = "rockchip,rv1108-gmac";
reg = <0x30200000 0x10000>;
@@ -704,6 +715,32 @@
};
};

+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <2 RK_PA0 3 &pcfg_pull_none>,
+ <2 RK_PA1 3 &pcfg_pull_none>,
+ <2 RK_PA2 3 &pcfg_pull_none>,
+ <2 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <2 RK_PA0 3 &pcfg_pull_none>,
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <2 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <2 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
gmac {
rmii_pins: rmii-pins {
rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
--
2.17.1