On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote:
MMU SCRATCH_DATA0 register is intended to cache task pgd. However in^ handle both
ARC700 SMP port, it has to be repurposed for reentrant interrupt
handling, while UP port doesn't. We currently ahandle boe usecases
maybe ':set spell' for changelog editing? ;-)