[linux-stable-rc:linux-5.4.y 5184/5947] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten

From: kernel test robot
Date: Mon Sep 06 2021 - 08:43:25 EST

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tree: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.4.y
head: 0aabc02724664358bdcea0cacee374b42c6dcfdb
commit: ca5a8ad84ba0d431daacd912da8b1d6594bc9e3c [5184/5947] drm/amd/display: Add vupdate_no_lock interrupts for DCN2.1
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git/commit/?id=ca5a8ad84ba0d431daacd912da8b1d6594bc9e3c
git remote add linux-stable-rc https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git
git fetch --no-tags linux-stable-rc linux-5.4.y
git checkout ca5a8ad84ba0d431daacd912da8b1d6594bc9e3c
# save the attached .config to linux build tree
make W=1 ARCH=i386

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[72]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[73]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[74]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[75]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[76]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
>> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: warning: initialized field overwritten [-Woverride-init]
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: (near initialization for 'irq_source_info_dcn21[77]')
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:242:39: note: in definition of macro 'vupdate_no_lock_int_entry'
242 | [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
| ^~
243 | IRQ_REG_ENTRY(OTG, reg_num,\
|
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:36:
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:221:29: warning: 'UVD0_BASE' defined but not used [-Wunused-const-variable=]
221 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:214:29: warning: 'USB0_BASE' defined but not used [-Wunused-const-variable=]
214 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:207:29: warning: 'UMC_BASE' defined but not used [-Wunused-const-variable=]
207 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:200:29: warning: 'THM_BASE' defined but not used [-Wunused-const-variable=]
200 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:193:29: warning: 'SMUIO_BASE' defined but not used [-Wunused-const-variable=]
193 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:186:29: warning: 'SDMA0_BASE' defined but not used [-Wunused-const-variable=]
186 | static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:179:29: warning: 'PCIE0_BASE' defined but not used [-Wunused-const-variable=]
179 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:172:29: warning: 'OSSSYS_BASE' defined but not used [-Wunused-const-variable=]
172 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:165:29: warning: 'NBIF0_BASE' defined but not used [-Wunused-const-variable=]
165 | static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:158:29: warning: 'MP1_BASE' defined but not used [-Wunused-const-variable=]
158 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:151:29: warning: 'MP0_BASE' defined but not used [-Wunused-const-variable=]
151 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:144:29: warning: 'MMHUB_BASE' defined but not used [-Wunused-const-variable=]
144 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:137:29: warning: 'L2IMU0_BASE' defined but not used [-Wunused-const-variable=]
137 | static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:130:29: warning: 'ISP_BASE' defined but not used [-Wunused-const-variable=]
130 | static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:123:29: warning: 'IOHC0_BASE' defined but not used [-Wunused-const-variable=]
123 | static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:116:29: warning: 'HDP_BASE' defined but not used [-Wunused-const-variable=]
116 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:109:29: warning: 'HDA_BASE' defined but not used [-Wunused-const-variable=]
109 | static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:102:29: warning: 'GC_BASE' defined but not used [-Wunused-const-variable=]
102 | static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:95:29: warning: 'FUSE_BASE' defined but not used [-Wunused-const-variable=]
95 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:88:29: warning: 'DPCS_BASE' defined but not used [-Wunused-const-variable=]
88 | static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:81:29: warning: 'DMU_BASE' defined but not used [-Wunused-const-variable=]
81 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:74:29: warning: 'DIO_BASE' defined but not used [-Wunused-const-variable=]
74 | static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:67:29: warning: 'DF_BASE' defined but not used [-Wunused-const-variable=]
67 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:60:29: warning: 'DBGU_IO0_BASE' defined but not used [-Wunused-const-variable=]
60 | static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
| ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:53:29: warning: 'CLK_BASE' defined but not used [-Wunused-const-variable=]
53 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:46:29: warning: 'ATHUB_BASE' defined but not used [-Wunused-const-variable=]
46 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:39:29: warning: 'ACP_BASE' defined but not used [-Wunused-const-variable=]
39 | static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },

vim +242 drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c

178
179 /* compile time expand base address. */
180 #define BASE(seg) \
181 BASE_INNER(seg)
182
183
184 #define SRI(reg_name, block, id)\
185 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 mm ## block ## id ## _ ## reg_name
187
188
189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
191 .enable_mask = \
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 .enable_value = {\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 },\
197 .ack_reg = SRI(reg2, block, reg_num),\
198 .ack_mask = \
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 .ack_value = \
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202
203
204
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
207 IRQ_REG_ENTRY(HPD, reg_num,\
208 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
209 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
211 .funcs = &hpd_irq_info_funcs\
212 }
213
214 #define hpd_rx_int_entry(reg_num)\
215 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
216 IRQ_REG_ENTRY(HPD, reg_num,\
217 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
218 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
220 .funcs = &hpd_rx_irq_info_funcs\
221 }
222 #define pflip_int_entry(reg_num)\
223 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
225 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
226 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
227 .funcs = &pflip_irq_info_funcs\
228 }
229
230 #define vupdate_int_entry(reg_num)\
231 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
232 IRQ_REG_ENTRY(OTG, reg_num,\
233 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
234 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
235 .funcs = &vblank_irq_info_funcs\
236 }
237
238 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
239 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
240 */
241 #define vupdate_no_lock_int_entry(reg_num)\
> 242 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
243 IRQ_REG_ENTRY(OTG, reg_num,\
244 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
245 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
246 .funcs = &vupdate_no_lock_irq_info_funcs\
247 }
248

---
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