Re: [PATCH v1 1/2] gpio: mlxbf2: Introduce IRQ support

[Andrew Lunn]

On Thu, Sep 16, 2021 at 03:48:51PM +0000, Asmaa Mnebhi wrote:
> > +	/* Enable PHY interrupt by setting the priority level */
> 
> This should be an abstract driver for a collection of GPIO lines.
> Yes, one of these GPIOs is used for the PHY, but the GPIO driver does not care. So please remove this comment.
> Asmaa>> Done
> 
> > +	val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
> > +	val |= BIT(offset);
> > +	writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
> 
> What exactly does this do? It appears to clear the interrupt, if i understand mlxbf2_gpio_irq_handler(). I don't know the GPIO framework well enough to know if this is correct. It does mean if the interrupt signal is active but masked, and you enable it, you appear to loose the interrupt? Maybe you want the interrupt to fire as soon as it is enabled?
> 
> Asmaa>>
> YU_GPIO_CAUSE_OR_CLRCAUSE - Makes sure the interrupt is initially cleared. Otherwise, we will not receive further interrupts.

If the interrupt status bit is set, as soon as you unmask the
interrupt, the hardware should fire the interrupt. At least, that is
how interrupt controllers usually work.

A typical pattern is that the interrupt fires. You mask it, ack it,
and then do what is needed to actually handle the interrupt. While
doing the handling, the hardware can indicate the interrupt again. But
since it is masked nothing happened. This avoids your interrupt handler
going recursive. Once the handler has finished, the interrupt is
unmasked. At this point it actually fires, triggering the interrupt
handler again.

Please also get your email client fixed. I wrap my emails at around 75
characters. Your mailer has destroyed it. Your text should also be
wrapped at about 75 characters.

	Andrew