[chenxing:msc313_mainlining 37/57] drivers/pinctrl/mstar/pinctrl-msc313.c:256:5: error: 'CONFIG_MACH_INFINITY' is not defined, evaluates to 0

[kernel test robot]

tree:   git://github.com/linux-chenxing/linux.git msc313_mainlining
head:   71c92cf0080ae69122be726bc4682b28a622e5ad
commit: c69c1259ec1bf7eb55a2eafb3facca3cc2c33be3 [37/57] pinctrl: mstar: msc313 pinctrl driver
config: x86_64-buildonly-randconfig-r002-20210920 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project c8b3d7d6d6de37af68b2f379d0e37304f78e115f)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/linux-chenxing/linux/commit/c69c1259ec1bf7eb55a2eafb3facca3cc2c33be3
        git remote add chenxing git://github.com/linux-chenxing/linux.git
        git fetch --no-tags chenxing msc313_mainlining
        git checkout c69c1259ec1bf7eb55a2eafb3facca3cc2c33be3
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

>> drivers/pinctrl/mstar/pinctrl-msc313.c:256:5: error: 'CONFIG_MACH_INFINITY' is not defined, evaluates to 0 [-Werror,-Wundef]
   #if CONFIG_MACH_INFINITY
       ^
   drivers/pinctrl/mstar/pinctrl-msc313.c:1543:5: error: 'CONFIG_MACH_INFINITY' is not defined, evaluates to 0 [-Werror,-Wundef]
   #if CONFIG_MACH_INFINITY
       ^
   2 errors generated.


vim +/CONFIG_MACH_INFINITY +256 drivers/pinctrl/mstar/pinctrl-msc313.c

   226	
   227	#define I2C1_PIN(_pin, _offset) MSTAR_PINCTRL_PIN(_pin, REG_I2C1_PULL_EN, _offset, \
   228			REG_I2C1_PULL_DIR, _offset, REG_I2C1_DRIVE, _offset, 1, i2c_drivestrengths)
   229	
   230	#define I2C1_PINS(_chipname) I2C1_PIN(PIN_##_chipname##_I2C1_SCL, 0), \
   231				     I2C1_PIN(PIN_##_chipname##_I2C1_SDA, 1)
   232	
   233	static const unsigned int sr_drivestrengths[] = {4, 8};
   234	#define SR_PIN_0(_pin, _offset) MSTAR_PINCTRL_PIN(_pin, REG_SR_PULL_EN0, _offset, \
   235			REG_SR_PULL_DIR0, _offset, REG_SR_DRIVE0, _offset, 1, sr_drivestrengths)
   236	#define SR_PIN_1(_pin, _offset) MSTAR_PINCTRL_PIN(_pin, REG_SR_PULL_EN1, _offset, \
   237			REG_SR_PULL_DIR1, _offset, REG_SR_DRIVE1, _offset, 1, sr_drivestrengths)
   238	
   239	#define SR_PINS(_chipname) SR_PIN_0(PIN_##_chipname##_SR_IO2, 2), \
   240				   SR_PIN_0(PIN_##_chipname##_SR_IO3, 3), \
   241				   SR_PIN_0(PIN_##_chipname##_SR_IO4, 4), \
   242				   SR_PIN_0(PIN_##_chipname##_SR_IO5, 5), \
   243				   SR_PIN_0(PIN_##_chipname##_SR_IO6, 6), \
   244				   SR_PIN_0(PIN_##_chipname##_SR_IO7, 7), \
   245				   SR_PIN_0(PIN_##_chipname##_SR_IO8, 8), \
   246				   SR_PIN_0(PIN_##_chipname##_SR_IO9, 9), \
   247				   SR_PIN_0(PIN_##_chipname##_SR_IO10, 10), \
   248				   SR_PIN_0(PIN_##_chipname##_SR_IO11, 11), \
   249				   SR_PIN_0(PIN_##_chipname##_SR_IO12, 12), \
   250				   SR_PIN_0(PIN_##_chipname##_SR_IO13, 13), \
   251				   SR_PIN_0(PIN_##_chipname##_SR_IO14, 14), \
   252				   SR_PIN_0(PIN_##_chipname##_SR_IO15, 15), \
   253				   SR_PIN_1(PIN_##_chipname##_SR_IO16, 0), \
   254				   SR_PIN_1(PIN_##_chipname##_SR_IO17, 1)
   255	
 > 256	#if CONFIG_MACH_INFINITY
   257	/* msc313/msc313e */
   258	/* pinctrl pins */
   259	static struct pinctrl_pin_desc msc313_pins[] = {
   260		MSC313_COMMON_PIN(ETH_RN),
   261		MSC313_COMMON_PIN(ETH_RP),
   262		MSC313_COMMON_PIN(ETH_TN),
   263		MSC313_COMMON_PIN(ETH_TP),
   264		MSC313_COMMON_PIN(FUART_RX),
   265		MSC313_COMMON_PIN(FUART_TX),
   266		MSC313_COMMON_PIN(FUART_CTS),
   267		MSC313_COMMON_PIN(FUART_RTS),
   268		MSC313_COMMON_PIN(I2C1_SCL),
   269		MSC313_COMMON_PIN(I2C1_SDA),
   270		PINCTRL_PIN(PIN_MSC313_SR_IO2,	"sr_io2"),
   271		PINCTRL_PIN(PIN_MSC313_SR_IO3,	"sr_io3"),
   272		PINCTRL_PIN(PIN_MSC313_SR_IO4,	"sr_io4"),
   273		PINCTRL_PIN(PIN_MSC313_SR_IO5,	"sr_io5"),
   274		PINCTRL_PIN(PIN_MSC313_SR_IO6,	"sr_io6"),
   275		PINCTRL_PIN(PIN_MSC313_SR_IO7,	"sr_io7"),
   276		PINCTRL_PIN(PIN_MSC313_SR_IO8,	"sr_io8"),
   277		PINCTRL_PIN(PIN_MSC313_SR_IO9,	"sr_io9"),
   278		PINCTRL_PIN(PIN_MSC313_SR_IO10,	"sr_io10"),
   279		PINCTRL_PIN(PIN_MSC313_SR_IO11,	"sr_io11"),
   280		PINCTRL_PIN(PIN_MSC313_SR_IO12,	"sr_io12"),
   281		PINCTRL_PIN(PIN_MSC313_SR_IO13,	"sr_io13"),
   282		PINCTRL_PIN(PIN_MSC313_SR_IO14,	"sr_io14"),
   283		PINCTRL_PIN(PIN_MSC313_SR_IO15,	"sr_io15"),
   284		PINCTRL_PIN(PIN_MSC313_SR_IO16,	"sr_io16"),
   285		PINCTRL_PIN(PIN_MSC313_SR_IO17,	"sr_io17"),
   286		MSC313_COMMON_PIN(SPI0_CZ),
   287		MSC313_COMMON_PIN(SPI0_CK),
   288		MSC313_COMMON_PIN(SPI0_DI),
   289		MSC313_COMMON_PIN(SPI0_DO),
   290		MSC313_COMMON_PIN(SD_CLK),
   291		MSC313_COMMON_PIN(SD_CMD),
   292		MSC313_COMMON_PIN(SD_D0),
   293		MSC313_COMMON_PIN(SD_D1),
   294		MSC313_COMMON_PIN(SD_D2),
   295		MSC313_COMMON_PIN(SD_D3),
   296		MSC313_COMMON_PIN(USB_DM),
   297		MSC313_COMMON_PIN(USB_DP),
   298	};
   299	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip