Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
From: Sharma, Deepak
Date: Tue Sep 21 2021 - 23:50:25 EST
Hi Rafael,
On 9/1/2021 5:45 AM, Rafael J. Wysocki wrote:
On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@xxxxxxx> wrote:
On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@xxxxxxx> wrote:
AMD CPU which support C3 shares cache. Its not necessary to flush the
caches in software before entering C3. This will cause performance drop
for the cores which share some caches. ARB_DIS is not used with current
AMD C state implementation. So set related flags correctly.
Signed-off-by: Deepak Sharma <deepak.sharma@xxxxxxx>
Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!
I might need to send subsequent patch for this. Can you please point me
to git and branch where this has been merged.
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
Still I am not able to see this patch merged on linux-next branch.
Thanks,
Deepak
---
arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 7de599eba7f0..62a5986d625a 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
*/
flags->bm_control = 0;
}
+ if (c->x86_vendor == X86_VENDOR_AMD) {
+ /*
+ * For all AMD CPUs that support C3, caches should not be
+ * flushed by software while entering C3 type state. Set
+ * bm->check to 1 so that kernel doesn't need to execute
+ * cache flush operation.
+ */
+ flags->bm_check = 1;
+ /*
+ * In current AMD C state implementation ARB_DIS is no longer
+ * used. So set bm_control to zero to indicate ARB_DIS is not
+ * required while entering C3 type state.
+ */
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
2.25.1