Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO
From: Jason Gunthorpe
Date: Thu Sep 23 2021 - 07:27:23 EST
On Thu, Sep 23, 2021 at 11:15:24AM +0100, Jean-Philippe Brucker wrote:
> So we can only tell userspace "No_snoop is not supported" (provided we
> even want to allow them to enable No_snoop). Users in control of stage-1
> tables can create non-cacheable mappings through MAIR attributes.
My point is that ARM is using IOMMU_CACHE to control the overall
cachability of the DMA
ie not specifying IOMMU_CACHE requires using the arch specific DMA
cache flushers.
Intel never uses arch specifc DMA cache flushers, and instead is
abusing IOMMU_CACHE to mean IOMMU_BLOCK_NO_SNOOP on DMA that is always
cachable.
These are different things and need different bits. Since the ARM path
has a lot more code supporting it, I'd suggest Intel should change
their code to use IOMMU_BLOCK_NO_SNOOP and abandon IOMMU_CACHE.
Which clarifies what to do here as uAPI - these things need to have
different bits and Intel's should still have NO SNOOP in the
name. What the no-snoop bit is called on other busses can be clarified
in comments if that case ever arises.
Jason