Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs

From: Sharma, Deepak
Date: Fri Sep 24 2021 - 01:42:41 EST

On 9/22/2021 5:47 AM, Rafael J. Wysocki wrote:
On Wed, Sep 22, 2021 at 5:50 AM Sharma, Deepak <deesharm@xxxxxxx> wrote:
Hi Rafael,

On 9/1/2021 5:45 AM, Rafael J. Wysocki wrote:
On Wed, Sep 1, 2021 at 4:14 AM Deepak Sharma <deesharm@xxxxxxx> wrote:
On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@xxxxxxx> wrote:
AMD CPU which support C3 shares cache. Its not necessary to flush the
caches in software before entering C3. This will cause performance drop
for the cores which share some caches. ARB_DIS is not used with current
AMD C state implementation. So set related flags correctly.

Signed-off-by: Deepak Sharma <deepak.sharma@xxxxxxx>
Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!
I might need to send subsequent patch for this. Can you please point me
to git and branch where this has been merged.
git:// linux-next
Still I am not able to see this patch merged on linux-next branch.
It was there, but got dropped before the merge window due to the
unclear next steps.

I'd rather see this resent along with the subsequent patch you were
talking about.
Thanks for the clarification. I will resend patch with subsequent changes which will have support for zen onward CPU's.