[PATCH 0/6] MIPS: ralink: fix PCI IO resources
From: Sergio Paracuellos
Date: Fri Sep 24 2021 - 17:11:46 EST
MIPs ralink need a special tratement regarding the way it handles PCI IO
resources. On MIPS I/O ports are memory mapped, so we access them using normal
load/store instructions. MIPS 'plat_mem_setup()' function does a call to
'set_io_port_base(KSEG1)'. There, variable 'mips_io_port_base'
is set then using this address which is a virtual address to which all
ports are being mapped. Ralink I/O space has a mapping of bus address
equal to the window into the mmio space, with an offset of IO start range
cpu address. This means that to have this working we need:
- linux port numbers in the range 0-0xffff.
- pci port numbers in the range 0-0xffff.
- io_offset being zero.
These means at the end to have bus address 0 mapped to IO range cpu address.
We need a way of properly set 'mips_io_port_base' with a virtually mapped
value of the IO cpu address.
This series do the following approach:
1) Revert two bad commit from a previous attempt of make this work .
2) Set PCI_IOBASE to mips 'mips_io_port_base'.
3) Allow architecture dependent 'pci_remap_iospace'.
4) Implement 'pci_remap_iospace' for MIPS.
5) Be sure IOBASE address for IO window is set with correct value.
More context about this series appoach in this mail thread .
Thanks in advance for your time.
Sergio Paracuellos (6):
Revert "MIPS: ralink: don't define PC_IOBASE but increase
Revert "staging: mt7621-pci: set end limit for 'ioport_resource'"
MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base'
PCI: allow architecture specific implementation of pci_remap_iospace()
MIPS: implement architecture dependent 'pci_remap_iospace()'
staging: mt7621-pci: properly adjust base address for the IO window
arch/mips/include/asm/mach-ralink/spaces.h | 4 +++-
arch/mips/include/asm/pci.h | 2 ++
arch/mips/pci/pci-generic.c | 9 +++++++++
drivers/pci/pci.c | 2 ++
drivers/staging/mt7621-pci/pci-mt7621.c | 4 +---
5 files changed, 17 insertions(+), 4 deletions(-)