Re: [RFC PATCH 05/13] x86/irq: Reserve a user IPI notification vector

From: Sohil Mehta
Date: Mon Sep 27 2021 - 15:08:12 EST

On 9/26/2021 5:39 AM, Thomas Gleixner wrote:
On Sat, Sep 25 2021 at 15:30, Thomas Gleixner wrote:
On Fri, Sep 24 2021 at 01:07, Thomas Gleixner wrote:
The obvious question is: What is the value of clearing UINV?

Absolutely none. That notification vector cannot be used for anything
else, so why would the OS be interested to see it ever? This is about
user space interupts, right?

UINV should be set _ONCE_ when CR4.UINTR is enabled and not be touched
by XSAVES/XRSTORS at all. Any delivery of this vector to the OS should
be considered a hardware bug.
After decoding the documentation (sigh) and staring at the implications of
keeping UINV armed, I can see the point vs. the UPID lifetime issue when
a task gets scheduled out and migrated to a different CPU.

I think you got it right. Here is my understanding of this.

The User-interrupt notification processing moves all the pending interrupts from UPID.PIR to the UIRR.

As you mentioned below, XSTATE is saved due to several reasons which saves the UIRR into memory. UIRR should no longer be updated after it has been saved.

XSAVES clears UINV is to stop detecting additional interrupts in the UIRR after it has been saved.

Not the most pretty solution, but as there needs to be some invalidation
which needs to be undone on return to user space it probably does not
matter much.

As the whole thing is tightly coupled to XSAVES/RSTORS we need to
integrate it into that machinery and not pretend that it's something
half independent.

I agree. Thank you for pointing this out.

That means we have to handle the setting of the SN bit in UPID whenever
XSTATE is saved either during context switch, when the kernel uses the
FPU or in other places (signals, fpu_clone ...). They all end up in
save_fpregs_to_fpstate() so that might be the place to look at.

 Yes. The current code doesn't do this. SN bit should be set whenever UINTR XSTATE is saved.

While talking about that: fpu_clone() has to invalidate the UINTR state
in the clone's xstate after the memcpy() or xsaves() operation.

Also the restore portion on the way back to user space has to be coupled
more tightly:

if (unlikely(ti_work & _TIF_UPID))
uintr_restore_upid(ti_work & _TIF_NEED_FPU_LOAD);
if (unlikely(ti_work & _TIF_NEED_FPU_LOAD))

I am assuming _TIF_UPID would be set everytime SN is set and XSTATE is saved.

apicid = __this_cpu_read(x86_cpu_to_apicid);

if (x2apic_enabled())
upid->ndst.x2apic = apicid;
upid->ndst.apic = apicid;

uintr_restore_upid(bool xrstors_pending)
// Update destination

// Do we need something stronger here?

clear_bit(SN, upid->status);

// Any SENDUIPI after this point sends to this CPU
// Any bit which was set in upid->pir after SN was set
// and/or UINV was cleared by XSAVES up to the point
// where SN was cleared above is not reflected in UIRR.

// As this runs with interrupts disabled the current state
// of upid->pir can be read and used for restore. A SENDUIPI
// which sets a bit in upid->pir after that read will send
// the notification vector which is going to be handled once
// the task reenables interrupts on return to user space.
// If the SENDUIPI set the bit before the read then the
// notification vector handling will just observe the same
// PIR state.

// Needs to be a locked access as there might be a
// concurrent SENDUIPI modiying it.
pir = read_locked(upid->pir);

if (xrstors_pending)) {
// Update the saved xstate for xrstors
current->xstate.uintr.uinv = UINTR_NOTIFICATION_VECTOR;

XSAVES saves the UINV value into the XSTATE buffer. I am not sure if we need this again. Is it because it could have been overwritten by calling XSAVES twice?

current->xstate.uintr.uirr = pir;

I believe PIR should be ORed. There could be some bits already set in the UIRR.

Also, shouldn't UPID->PIR be cleared? If not, we would detect these interrupts all over again during the next ring transition.

} else {
// Manually restore UIRR and UINV
wrmsrl(IA32_UINTR_RR, pir);
I believe read-modify-write here as well.
misc.val64 = 0;
misc.uittsz = current->uintr->uittsz;
wrmsrl(IA32_UINTR_MISC, misc.val64);

Thanks! This helps reduce the additional MSR read.


That's how I deciphered the documentation and I don't think this is far
from reality, but I might be wrong as usual.


Thank you for the simplification. This is very helpful.