Re: [PATCH] powerpc/40x: Map 32Mbytes of memory at startup

[cp]

hi,
this is my second patch-test report.

Today I have successfully tested Christophe Leroy's patch.

Attached a cleaned patch. With the previous one the kernel booted, but
there was a line missing.

I have also tested two different kernels with success

both kernel sizes were ~9.4MB
the Entry Point was always 0x00901b00

used toolchain:
- powerpc-unknown-linux-gnu-binutiles-v2.34
- powerpc-unknown-linux-gnu-gcc-v9.3.0

host:
- macmini-intel, Gentoo cross-compiler, 32bit userland

target:
- AMCC PPC405GP

wrapper:
- cuboot

Applied to
- kernel-v5.2.1-vanilla
- kernel-v5.7.19-vanilla

Attached I report here is the difference between the original file and mine.

Thanks guys!
Carlo

-----------------------
map 32MB of ram rather than 16MB
--- arch/powerpc/kernel/head_40x.S.original     2021-09-28
00:07:27.768000000 -0000
+++ arch/powerpc/kernel/head_40x.S      2021-09-28 00:07:27.760000000 -0000
@@ -25,6 +25,7 @@
  *      Kernel execution entry point code.
  */

+
 #include <linux/init.h>
 #include <asm/processor.h>
 #include <asm/page.h>
@@ -842,17 +843,33 @@
        mtspr   SPRN_PID,r0
        sync

-       /* Configure and load one entry into TLB slots 63 */
-       clrrwi  r4,r4,10                /* Mask off the real page number */
-       ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
-
-       clrrwi  r3,r3,10                /* Mask off the effective page number */
-       ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
-
-        li      r0,63                    /* TLB slot 63 */
-
-       tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
-       tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
+        /*
+         * Configure and load two entries into TLB slots 62 and 63.
+         *     TLB 62 is used for first 16M page
+         *     TLB 63 is for the second 16M page
+         * In case we are pinning TLBs, these are reserved in by
+         * the other TLB functions.
+         * If not reserved, then it doesn't matter where they are loaded.
+         */
+        clrrwi r4,r4,10                 /* Mask off the real page number */
+        ori    r4,r4,(TLB_WR | TLB_EX)  /* Set the write and execute bits */
+
+        clrrwi r3,r3,10                 /* Mask off the effective
page number */
+        ori    r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
+
+        li     r0,62                    /* TLB slot 62 */
+
+        tlbwe  r4,r0,TLB_DATA           /* Load the data portion of
the entry */
+        tlbwe  r3,r0,TLB_TAG            /* Load the tag portion of the entry */
+
+        addis  r4, r4, 0x0100           /* Map next 16 Mentries */
+        addis  r3, r3, 0x0100
+
+        li      r0,63                   /* TLB slot 63 */
+
+        /* Load up the kernel context */
+        tlbwe   r4,r0,TLB_DATA          /* Load the data portion of
the entry */
+        tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */

        isync




On Mon, 27 Sept 2021 at 12:35, Christophe Leroy
<christophe.leroy@xxxxxxxxxx> wrote:
>
> As reported by Carlo, 16Mbytes is not enough with modern kernels
> that tend to be a bit big, so map another 16M page at boot.