Re: [PATCH V2 2/2] dt-bindings: riscv: Add svpbmt in cpu mmu-type property

[Guo Ren]

On Tue, Sep 28, 2021 at 3:32 AM Atish Patra <atishp@xxxxxxxxxxxxxx> wrote:
>
>
>
> On Thu, Sep 23, 2021 at 10:22 AM <guoren@xxxxxxxxxx> wrote:
>>
>> From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
>>
>> Previous patch has added svpbmt in arch/riscv and changed the
>> DT mmu-type. Update dt-bindings related property here.
>>
>
> This is the first of many small ISA extensions to be added to RISC-V.
> Should we think about a generic DT property and parsing framework for all hart related ISA extensions now instead of adding
> to the existing mmu-type.
Change existing mmu-type will cause a compatible problem. If we still
keep current solution, I think it's still okay. eg:
mmu-type = "riscv,sv39,svpbmt,svnapot,svinval";

Or, if we still want to change, how:
mmu-type = "riscv,sv39";
mmu-type-ext = "svpbmt,svnapot,svinval"

Still keep mmu-type like before.

>
> We will soon need to add the CMO extensions as well.
>
>>
>> Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
>> Cc: Anup Patel <anup@xxxxxxxxxxxxxx>
>> Cc: Palmer Dabbelt <palmer@xxxxxxxxxxx>
>> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
>> ---
>>  Documentation/devicetree/bindings/riscv/cpus.yaml | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> index e534f6a7cfa1..5eea9b47dfc6 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> @@ -48,15 +48,18 @@ properties:
>>
>>    mmu-type:
>>      description:
>> -      Identifies the MMU address translation mode used on this
>> -      hart.  These values originate from the RISC-V Privileged
>> -      Specification document, available from
>> +      Identifies the MMU address translation mode and page based
>> +      memory type used on used on this hart.  These values originate
>> +      from the RISC-V Privileged Specification document, available
>> +      from
>>        https://riscv.org/specifications/
>>      $ref: "/schemas/types.yaml#/definitions/string"
>>      enum:
>>        - riscv,sv32
>>        - riscv,sv39
>> +      - riscv,sv39,svpbmt
>>        - riscv,sv48
>> +      - riscv,sv48,svpbmt
>>        - riscv,none
>>
>>    riscv,isa:
>> --
>> 2.25.1
>>
>>
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>
>
>
> --
> Regards,
> Atish



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/