Re: [PATCH] clk: renesas: r8a779[56]x: add MLP clock

[Geert Uytterhoeven]

Hi Nikita,

On Thu, Oct 7, 2021 at 10:09 PM Nikita Yushchenko
<nikita.yoush@xxxxxxxxxxxxxxxxxx> wrote:
> > These additions look fine to me.  I'm only wondering about the
> > actual parent clocks, which are not well-documented in the Hardware
> > User's Manual.
> > It does say that MLP uses the Audio main bus (AXI).
> > The related AUDIO-DMAC uses S1D2, which runs at 266 MHz, while S2D1
> > runs at 400 MHz?
>
> This patch was included in this form into Renesas BSP for years.
>
> Indeed, the information on the parent clock is missing in the manual, and can be inexact here. I've sent
> a question to our contact at Renesas but not sure they will reply.
>
> But, AFAIU, these parent clocks are not software-controlled, so having them wrong does not result in any
> issues other than inexact information exported via sysfs/debugfs.

True.  So in case we don't get feedback, I'll take this patch as-is.

> > BTW, do you plan to enable full support for MLP in the upstream kernel?
>
> Yes, we are upstreaming full KF board support now.

I'm happy to hear that, thanks a lot!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds